Abstract
The problem of discovering previously unknown frequent patterns in time series, also called motifs, has been recently introduced. A motif is a subseries pattern that appears a significant number of times. Results demonstrate that motifs may provide valuable insights about the data and have a wide range of applications in data mining tasks. The main motivation for this study was the need to mine time series data from protein folding/unfolding simulations. We propose an algorithm that extracts approximate motifs, i.e. motifs that capture portions of time series with a similar and eventually symmetric behavior. Preliminary results on the analysis of protein unfolding data support this proposal as a valuable tool. A.dditional experiments demonstrate that the application of utility of our algorithm is not limited to this particular problem. Rather it can be an interesting tool to be applied in many real world problems.

Abstract
Distributed manufacturing control systems, such as Holonic Control Systems (HCSs), are difficult to apprehend and to design, due to the presence of many autonomous, concurrent and asynchronous activities. A formal specification methodology allowing to understand, to synthesise the system specifications and to validate the correctness of their models would play a key role in its design and later in its implementation. This paper presents an approach to the formal specification of HCSs based on high-level Petri nets. The proposed approach is tested in the specification of the ADACOR HCS. Copyright © 2006 Inderscience Enterprises Ltd.

Abstract
The growth in FPGA capacity and the inclusion of embedded arithmetic cores has enabled the use of these devices for general purpose floating-point computing. Despite their clock rate handicap with respect to contemporary general-purpose processors, these devices can be field-programmable to meet the precision requirements and operator-level parallelism of a specific computation. In this paper we describe and evaluate the performance of dual-precision, pipelined, floating-point arithmetic cores for addition, multiplication and division. Each of these arithmetic cores can be switched at run-time to perform either one double-precision operation, or with the same hardware resources, perform two single-precision operations. We also implemented quad-precision cores which can be switched to perform either one quad-precision operation or two double-precision operations. As an application of these cores, we describe and evaluate the performance potential of a custom, but flexible, vector processing units as part of a system-level architecture targeting a Xilinx Virtex-II Pro™ 100 FPGA device connected to multiple SRAM banks. ©2006 IEEE.

Abstract
In this paper we extend M. Lyubich's recent results on the global hyperbolicity of renormalization of quadratic-like germs to the space of C-r unimodal maps with quadratic critical point. We show that in this space the bounded-type limit sets of the renormalization operator have an invariant hyperbolic structure provided r >= 2 + alpha with alpha close to one. As an intermediate step between Lyubich's results and ours, we prove that the renormalization operator is hyperbolic in a Banach space of real analytic maps. We construct the local stable manifolds and prove that they form a continuous lamination whose leaves are C-1 codimension one, Banach submanifolds of the ambient space, and whose holonom is C1+beta for some beta > 0. We also prove that the global stable sets are C-1 immersed (codimension one) submanifolds as well, provided r >= 3 + alpha with alpha close to one. As a corollary, we deduce that in generic, one-parameter families of C-r unimodal maps, the set of parameters corresponding to infinitely renormalizable maps of bounded combinatorial type is a Cantor set with Hausdorff dimension less than one(1).

Abstract
Configurable architectures, with multiple independent on-chip RAM modules, offer the unique opportunity to exploit inherent parallel memory accesses in a sequential program by not only tailoring the number and configuration of the modules in the resulting hardware design but also the accesses to them. In this paper we explore the possibility of array replication for loop computations that is beyond the reach of traditional privatization and parallelization analyses. We present a compiler analysis that identifies portions of array variables that can be temporarily replicated within the execution of a given loop iteration, enabling the concurrent execution of statements or even non-perfectly nested loops. For configurable architectures where array replication is essentially free in terms of execution time, this replication enables not only parallel execution but also reduces or even eliminates memory contention. We present preliminary experiments applying the proposed technique to hardware designs for commercially available FPGA devices. © 2006 Springer-Verlag Berlin Heidelberg.

Abstract
This paper presents the performed steps to design an Artificial Neural Network (ANN) tool, able to evaluate, within the framework of on-line security assessment, the dynamic security of interconnected power systems having an increased penetration of wind power production. This approach exploits functional knowledge generated off-line, the Linear Regression (LR) variable selection stepwise method to perform automatic Feature Subset Selection (FSS) and ANN to provide a way for fast evaluation of the system security degree. In order to choose the best input/output set of variables for the ANN tool, a comparative analysis is performed, regarding the obtained predicting error, by performing a statistical hypothesis test. The reduced error results confirm the feasibility and quality of the derived security structures.