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Publicações

2015

Electricity price forecast using Combinatorial Neural Network trained by a new stochastic search method

Autores
Abedinia, O; Amjady, N; Shafie Khah, M; Catalao, JPS;

Publicação
ENERGY CONVERSION AND MANAGEMENT

Abstract
Electricity price forecast is key information for successful operation of electricity market participants. However, the time series of electricity price has nonlinear, non-stationary and volatile behaviour and so its forecast method should have high learning capability to extract the complex input/output mapping function of electricity price. In this paper, a Combinatorial Neural Network (CNN) based forecasting engine is proposed to predict the future values of price data. The CNN-based forecasting engine is equipped with a new training mechanism for optimizing the weights of the CNN. This training mechanism is based on an efficient stochastic search method, which is a modified version of chemical reaction optimization algorithm, giving high learning ability to the CNN. The proposed price forecast strategy is tested on the real-world electricity markets of Pennsylvania-New Jersey-Maryland (PJM) and mainland Spain and its obtained results are extensively compared with the results obtained from several other forecast methods. These comparisons illustrate effectiveness of the proposed strategy.

2015

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

Autores
Al Farisi, B; Heyse, K; Bruneel, K; Cardoso, J; Stroobandt, D;

Publicação
DESIGN AUTOMATION FOR EMBEDDED SYSTEMS

Abstract
Using dynamic partial reconfiguration (DPR), several circuits can be time-multiplexed on the same FPGA region, saving considerable area compared to an implementation without DPR. However, the long reconfiguration time to switch between circuits remains a significant problem. In this work we show that it is possible to significantly reduce this overhead when the number of circuits is limited. We lower the DPR overhead by reducing the number of configuration bits that needs to be reconfigured. This is achieved by keeping a (predetermined) part of the configuration frames of the DPR region constant/static for all circuits and, consequentially, sharing this part of the configuration between all the circuits. We show that this can be done maintaining the possibility to implement completely unrelated circuits in the DPR region. An extension of the Pathfinder algorithm, called StaticRoute, is presented. It is able to route the nets of the different circuits simultaneously in such a way that the routing of the different circuits is the same in the static part and may only differ in the dynamic part. Our approach is evaluated on the architecture of a commercially available SRAM-based FPGA. We explore how the static part in the configuration memory is best chosen and investigate the associated impact on maximum operating clock frequency as the number of circuits increases. Our experiments show that it is possible to make 50 % of the routing configuration static and therefore reduce the routing reconfiguration time by 50 %, without a significant impact on maximum clock frequency of the circuits. This corresponds to a reduction of total reconfiguration time of 34 %.

2015

A Special-Purpose Language for Implementing Pipelined FPGA-based Accelerators

Autores
de Oliveira, CB; Menotti, R; Cardoso, JMP; Marques, E;

Publicação
2015 18th Forum on Specification and Design Languages (FDL)

Abstract
A common use for Field-Programmable Gate Arrays (FPGAs) is the implementation of hardware accelerators. A way of doing so is to specify the internal logic of such accelerators by using Hardware Description Languages (HDLs). However, HDLs rely on the expertise of developers and their knowledge about hardware development with FPGAs. Regarding this, efforts have been focused on developing High-level Synthesis (HLS) tools in an attempt to increase the overall abstraction level required for using FPGAs. However, the solutions presented by such tools are commonly considered inefficient in comparison to the ones achieved by a specialized hardware designer. An alternative solution to program FPGAs is the use of Domain-Specific Languages (DSLs), as they can provide higher abstraction levels than HDLs still allowing the developers to deal with specific issues leading to more efficient designs and not always covered by HLS tools. In this paper we present our recent work on a DSL named LALP (Language for Aggressive Loop Pipelining), which has been developed focusing on the development of FPGA-based, aggressively pipelined, hardware accelerators. We present the recent LALP extensions and the challenges we are facing regarding to the compilation of LALP to FPGAs.

2015

Stable Operation of Grid-Interfacing Converter during the Operation of Active Power Filters in Power Grids

Autores
Pouresmaeil, E; Mehrasa, M; Shokridehaki, MA; Shafie khah, M; Rodrigues, EMG; Catalao, JPS;

Publicação
PROCEEDINGS 2015 9TH INTERNATIONAL CONFERENCE ON CAMPATIBILITY AND POWER ELECTRONICS (CPE)

Abstract
This paper introduces a control strategy for assessing the role of shunt active power filters (SAPF) in electrical power networks. The proposed control scheme is based on the Lyapunov control theory and defines a stable operating region for the interfaced converter during the integration with utility grid. The compensation of instantaneous variations of reference current components in the control loop of SAPF in ac-side, and dc-link voltage oscillations in dc-side of the proposed model, is considered accurately, which is the main contribution of this work in comparison with the other potential control approaches. The proposed control scheme can confirm the injection of all the harmonic current components and reactive power of grid-connected loads with a fast dynamic response, and a unity power factor between the grid currents and voltages. An extensive simulation study is performed, assessing the effectiveness of the proposed control plan in the utilization of SAPF in power networks.

2015

PH2: A public database for the analysis of dermoscopic images

Autores
Mendoncã, TF; Ferreira, PM; Marcãl, ARS; Barata, C; Marques, JS; Rocha, J; Rozeira, J;

Publicação
Dermoscopy Image Analysis

Abstract
Skin cancer represents a serious public health problem because of its increasing incidence and subsequent mortality. Among skin cancers, malignant melanoma is by far the most deadly form. Because the early detection of melanoma significantly increases the survival rate of the patient, several noninvasive imaging techniques, such as dermoscopy, have been developed to aid the screening process [1]. Dermoscopy involves the use of an optical instrument paired with a powerful lighting system, allowing the examination of skin lesions in a higher magnification. Therefore, dermoscopic images provide a more detailed view of the morphological structures and patterns than normally magnified images of the skin lesions [1, 2]. However, the visual interpretation and examination of dermoscopic images can be a time-consuming task and, as shown by Kittler et al. [3], the diagnosis accuracy of dermoscopy significantly depends on the experience of the dermatologists. Several medical diagnosis procedures have been introduced in order to guide dermatologists and other health care professionals, for example, pattern analysis, the ABCD rule, the 7-point checklist, and the Menzies method. A number of dermoscopic criteria (i.e., asymmetry, border, colors, differential structures) have to be assessed in these methods to produce the final clinical diagnosis. However, the diagnosis of skin lesions is still a challenging task, even using these medical procedures, mainly due to the subjectivity of clinical interpretation and lack of reproducibility [1, 2]. © 2016 by Taylor and Francis Group, LLC.

2015

Monitoring for a Decidable Fragment of MTL-?

Autores
Pedro, AD; Pereira, D; Pinho, LM; Pinto, JS;

Publicação
RUNTIME VERIFICATION, RV 2015

Abstract
Temporal logics targeting real-time systems are traditionally undecidable. Based on a restricted fragment of MTL-integral, we propose a new approach for the runtime verification of hard real-time systems. The novelty of our technique is that it is based on incremental evaluation, allowing us to effectively treat duration properties (which play a crucial role in real-time systems). We describe the two levels of operation of our approach: offline simplification by quantifier removal techniques; and online evaluation of a three-valued interpretation for formulas of our fragment. Our experiments show the applicability of this mechanism as well as the validity of the provided complexity results.

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