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Publicações

Publicações por HumanISE

2024

A Scoping Review of the Use of Blockchain and Machine Learning in Medical Imaging Applications

Autores
Pavao, J; Bastardo, R; Rocha, NP;

Publicação
GOOD PRACTICES AND NEW PERSPECTIVES IN INFORMATION SYSTEMS AND TECHNOLOGIES, VOL 2, WORLDCIST 2024

Abstract
This scoping review systematizes the current research related to the use of both blockchain and machine learning techniques in medical imaging applications. A systematic electronic search was performed, and twenty-five studies were included in the review. These studies aimed to use blockchain and machine learning techniques to provide (i) efficient security mechanisms to support the communication of medical imaging data, (ii) aggregation of distributed medical imaging data to train machine learning algorithms, and (iii) machine learning algorithms based on federated learning strategies. Among the ten machine learning techniques identified in the included studies, Convolutional Neural Network was the most representative (i.e., 44% of the studies). Moreover, Artificial Neural Network, Capsule Network, Deep Neural Network, Gated Recurrent Units, and Neural Network were machine learning techniques used by more than one study. Although the included studies developed algorithms with potential impact in clinical practice, it must be noted that they did not discuss the generalizability of their algorithms in real-world clinical conditions.

2024

Towards a Rust-Like Borrow Checker for C

Autores
Silva, T; Correia, P; Sousa, L; Bispo, J; Carvalho, T;

Publicação
ACM Transactions on Embedded Computing Systems

Abstract
Memory safety issues in C are the origin of various vulnerabilities that can compromise a program’s correctness or safety from attacks. We propose an approach to tackle memory safety by replicating Rust’s Mid-level Intermediate Representation (MIR) Borrow Checker. Our solution uses static analysis and successive source-to-source code transformations to be composed upstream of the compiler, ensuring maximal compatibility with existing build systems. This allows us to apply the memory safety guarantees of the rustc compiler to C code with fewer changes than a rewrite in Rust. In this work, we present a comprehensive study of Rust’s efforts towards ensuring memory safety, and describe the theoretical basis for a C borrow checker, alongside a proof-of-concept that was developed to demonstrate its potential. We have evaluated the prototype on the CHStone and bzip2 benchmarks. This prototype correctly identified violations of the ownership and aliasing rules, and exposed incompatibilities between such rules and common C patterns, which can be addressed in future work.

2024

Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study

Autores
Henriques, M; Bispo, J; Paulino, N;

Publicação
PROCEEDINGS OF THE RAPIDO 2024 WORKSHOP, HIPEAC 2024

Abstract
Hardware specialization is seen as a promising venue for improving computing efficiency, with reconfigurable devices as excellent deployment platforms for application-specific architectures. One approach to hardware specialization is via the popular RISC-V, where Instruction Set Architecture (ISA) extensions for domains such as Edge Artifical Intelligence (AI) are already appearing. However, to use the custom instructions while maintaining a high (e.g., C/C++) abstraction level, the assembler and compiler must be modified. Alternatively, inline assembly can be manually introduced by a software developer with expert knowledge of the hardware modifications in the RISC-V core. In this paper, we consider a RISC-V core with a vectorization and streaming engine to support the Unlimited Vector Extension (UVE), and propose an approach to automatically transform annotated C loops into UVE compatible code, via automatic insertion of inline assembly. We rely on a source-to-source transformation tool, Clava, to perform sophisticated code analysis and transformations via scripts. We use pragmas to identify code sections amenable for vectorization and/or streaming, and use Clava to automatically insert inline UVE instructions, avoiding extensive modifications of existing compiler projects. We produce UVE binaries which are functionally correct, when compared to handwritten versions with inline assembly, and achieve equal and sometimes improved number of executed instructions, for a set of six benchmarks from the Polybench suite. These initial results are evidence towards that this kind of translation is feasible, and we consider that it is possible in future work to target more complex transformations or other ISA extensions, accelerating the adoption of hardware/software co-design flows for generic application cases.

2024

A C Subset for Ergonomic Source-to-Source Analyses and Transformations

Autores
Matos, JN; Bispo, J; Sousa, LM;

Publicação
PROCEEDINGS OF THE RAPIDO 2024 WORKSHOP, HIPEAC 2024

Abstract
Modern compiled software, written in languages such as C, relies on complex compiler infrastructure. However, developing new transformations and improving existing ones can be challenging for researchers and engineers. Often, transformations must be implemented bymodifying the compiler itself, which may not be feasible, for technical or legal reasons. Source-to-source compilers make it possible to directly analyse and transform the original source, making transformations portable across different compilers, and allowing rapid research and prototyping of code transformations. However, this approach has the drawback of exposing the researcher to the full breadth of the source language, which is often more extensive and complex than the IRs used in traditional compilers. In this work, we propose a solution to tame the complexity of the source language and make source-to-source compilers an ergonomic platform for program analysis and transformation. We define a simpler subset of the C language that can implement the same programs with fewer constructs and implement a set of sourceto-source transformations that automatically normalise the input source code into equivalent programs expressed in the proposed subset. Finally, we implement a function inlining transformation that targets the subset as a case study. We show that for this case study, the assumptions afforded by using a simpler language subset greatly improves the number of cases the transformation can be applied, increasing the average success rate from 37%, before normalisation, to 97%, after normalisation. We also evaluate the performance of several benchmarks after applying a naive inlining algorithm, and obtained a 12% performance improvement in certain applications, after compiling with the flag O2, both in Clang and GCC, suggesting there is room for exploring source-level transformations as a complement to traditional compilers.

2024

15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2024, Munich, Germany, January 18, 2024

Autores
Bispo, J; Xydis, S; Curzel, S; Sousa, LM;

Publicação
PARMA-DITAM

Abstract

2024

A DSL and MLIR Dialect for Streaming and Vectorisation

Autores
da Silva, MC; Sousa, L; Paulino, N; Bispo, J;

Publicação
APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2024

Abstract
This work addresses the contemporary challenges in computing, caused by the stagnation of Moore's Law and Dennard scaling. The shift towards heterogeneous architectures necessitates innovative compilation strategies, prompting initiatives like the Multi-Level Intermediate Representation (MLIR) project, where progressive code lowering can be achieved through the use of dialects. Our work focuses on developing an MLIR dialect capable of representing streaming data accesses to memory, and Single Instruction Multiple Data (SIMD) vector operations. We also propose our own Structured Representation Language (SRL), a Design Specific Language (DSL) to serve as a precursor into the MLIR layer and subsequent inter-operation between new and existing dialects. The SRL exposes the streaming and vector computational concepts to a higher-level, and serves as intermediate step to supporting code generation containing our proposed dialect from arbitrary input code, which we leave as future work. This paper presents the syntaxes of the SRL DSL and of the dialect, and illustrates how we aim to employ them to target both General-Purpose Processors (GPPs) with SIMD co-processors and custom hardware options such as Field-Programmable Gate Arrayss (FPGAs) and Coarse-Grained Re-configurable Arrays (CGRAs).

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