Abstract
This paper presents a description of the image generation sub-system developed to allow the presentation of realistic visual feedback in interactive visual simulation with large scene databases. The developed image generator applies all the standard state-of-art image generation algorithms aimed to real-time interactive simulation. Some of these important algorithms are also explained in this document. I addition, some innovative optimization techniques like the hierarchical back face rejection of objects, the visibility preprocessing and the automatic optimization of levels-of-detail are being developed and detailed in this paper. These techniques will allow a better use of any image generation system and improve significantly the visualization of huge scene databases even in high-end graphics architectures.

Abstract

Abstract

Abstract
The COBIP UR4003 Project is running under the EC Telematics Application Programme and aims at demonstrating the usage of workflow tools in the management of telework decentralized activities. This paper presents an overview of the COBIP system, and its pilot implementation at TECNOTRON head offices in Lisbon.

Abstract

Abstract
This paper presents a new approach to synthesize to reconfigurable hardware (HW) user-specified regions of a program, under the assumption of "virtual HW" support. The automation of this approach is supported by a compiler front-end and by an HW compiler under development. The front-end starts from the Java bytecodes and, therefore, supports any language that can be compiled to the JVM (Java Virtual Machine) model. It extracts from the bytecodes all the dependencies inside and between basic blocks. This information is stored in representation graphs more suitable to efficiently exploit the existent parallelism in the program than those typically used in high-level synthesis. From the intermediate representations the HW compiler exploits the temporal partitions at the behavior level, resolves memory access conflicts, and generates the VHDL descriptions at register-transfer level that will be mapped into the reconfigurable HW devices.