Abstract
It is understood that Collaborative Work plays an important role in today's organizations lift cycle. On the other hand, any decision that may involve a set of decision makers is, by itself, quite complex. It is under this umbrella that it will be presented the VirtualECare project, that contemplates art intelligent multi-agent system able to monitor, interact and serve its customers in need of (health)care services. We will center our attention oil the system group decision and argumentation modules, which use idea generation techniques and resort to argumentation to exchange and justify belief and choice. At the end, a prototype will be presented.

Abstract
Collaborative Work plays an important role in today's organizations and normally in areas where decisions must be made. However, any decision that involves a collective or group of decision makers is, by itself, complex. In this work we present the VirtualECare project, built in terms of an intelligent multi-agent system able to monitor, interact and serve its customers, which are, normally, in need of care services, and assisted with tools based on open standards, like OSGi an R-OSGi.

Abstract
Researchers are giving special attention to innovative healthcare projects in order to reduce medical service costs and to deal with the population ageing. The Virtual e-Care was born taking those goals in mind. An intelligent and proactive system has been prototyped, Supporting group decision making techniques, idea generation, argumentation and the quantification of the quality of information. In this paper it is simulated a virtual Assisted Living Environment, based in a solid agent-based architecture. Special attention is given to the monitoring system.

Abstract

Abstract
Coarse-grained reconfigurable architectures have proven their value as programmable accelerators for general purpose processors. For early evaluation of those architectures, we need an approach able to exploit and retarget different Processing Elements (PEs) while maintaining the same compilation flow. Bearing in mind those aspects, this paper describes an approach able to map, evaluate and generate reconfigurable architectures based on an array of PEs. We use Rewriting Logic to map computations described by imperative programming languages to the PEs of the target architecture, a VHDL generation step to prototype the architectures being evaluated, and a clock cycle-based simulator to achieve first assessments about the performance of those architectures. In order to show the potential of our approach, we present results of 1-D coarse-grained reconfigurable arrays as accelerator softcores implemented in an FPGA, and the effects of different PE's structures and complexities.

Abstract