Abstract
In this work we investigate how different machine settings for a hardware Distributed Shared Memory (DSM) architecture affect the performance of parallel logic programming (PLP) systems. We use execution-driven simulation of a DASH-like multiprocessor to study the impact of the cache block size, the cache size, the network bandwidth, the write buffer size, and the coherence protocol on the performance of Andorra-I, a PLP system capable of exploiting implicit parallelism in Prolog programs. Among several other observations, we find that PLP systems favour small cache blocks regardless of the coherence protocol, while they favour large cache sizes only in the case of invalidate-based coherence. We conclude that the cache block size, the cache size, the network bandwidth, and the coherence protocol have a significant impact on the performance, while the size of the write buffer is somewhat irrelevant.

Abstract

Abstract

Abstract
In this work we investigate how Distributed Shared Memory (DSM) architectures affect performance of or-parallel logic programming systems and how this performance approaches that of conventional C systems. Our work concentrates on basic performance, scalability, and programmability. We use execution-driven simulation of a hardware DSM (DASH) to investigate the access patterns and caching behaviour exhibited by parallel C programs and by Aurora, a parallel logic programming system capable of exploiting implicit parallelism in Prolog programs. Aurora was originally written to run on bus-based shared-memory platforms. © Springer-Verlag Berlin Heidelberg 1999.

Abstract
We propose a simple model of distribution for mobile processes, independent of the underlying calculus. Conventional processes compute within sites; inter-site computation is achieved by message sending and object migration, both obeying a lexical scope. We focus on the semantics of networks, on programming practice, and on physical realization with current technology. ©1998 Published by Elsevier Science B.V.

Abstract
One of the most important advantages of logic programming systems is that they allow the transparent exploitation of parallelism. The different forms of parallelism available and the complex nature of logic programming applications present interesting problems to both the users and the developers of these systems. Graphical visualisation tools can give a particularly important contribution, as they are easier to understand than text based tools, and allow both for a general overview of an execution and for focusing on its important details. Towards these goals, we propose VisAll, anew tool to visualise the parallel execution of logic programs. VisAll benefits from a modular design centered in a graph that represents a parallel execution. A main graphical shell commands the different modules and presents VisAll as an unified system. Several input components, or translators, support the well-known VisAndor and VACE trace formats, plus a new format designed for independent and-parallel plus or-parallel execution in the SEA. Several output components, or visualisers, allow for different visualisations of the same execution.