Abstract
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.

Abstract
As RISC-V platforms become a target for real-time systems it is crucial to ensure and effect performance analysis to make sure that these systems meet the respective time constraints while also perform reliably. To achieve these goals, performance monitoring becomes a critical aspect, especially when considering resource-constrained environments where efficient resource usage is required. This paper focuses on the study and development of a solution to simplify the interaction with machine-level privileged counters and registers, considering two essential non-functional requirements (NFRs): low-overhead access to performance metrics and low memory API usage. The provided solution allows developers to retrieve and analyse performance data directly from user-level space with a simplified interface, while providing feedback for application optimization, isolation, and improved system reliability. The demonstrated results showcase how our approach meets the two NFRs and its potential in terms of customization for the target platform.