Abstract
The Physical layer architectures for the next generation of wireless devices will be characterized by a high degree of flexibility for real-time adaptation to communication conditions variability. OFDM-based architectures are strong candidates for the Physical layer implementation in 5G systems and one of the most important baseband processing operations required by this waveform is the Fast Fourier Transform (FFT). This paper proposes a dynamically reconfigurable FFT processor supporting FFT sizes and throughputs required by the most widely used wireless standards. The FFT reconfiguration was achieved by means of FPGA-based Dynamic Partial Reconfiguration (DPR) techniques, which enables run-time FFT size adaptation according to communication requirements and better resource utilization. The impact of DPR in terms of reconfiguration time and power consumption overhead was evaluated. The obtained results encourage the exploitation of DPR techniques to implement reconfigurable hardware infrastructures for OFDM baseband processing engines.

Abstract
As the number of wireless devices, services, communication standards and respective modes of operation rapidly grows, the design of reconfigurable digital baseband processing systems for radio devices becomes more important and challenging. Long Term Evolution (LTE) is among the most relevant wireless systems in 4G communications and its waveform is OFDM-based. According to the LTE mode of operation, OFDM parameters may change and influence baseband processing operations. This paper presents a dynamically reconfigurable LTE-compliant OFDM modulator for Downlink transmission able to adapt its internal hardware organization on-demand according to the digital modulation scheme and OFDM parameters, such as number of data subcarriers, IFFT size, Cyclic Prefix and window length. System reconfiguration is performed by employing FPGA-based Dynamic Partial Reconfiguration (DPR) techniques. The worst-case DPR latencies measured are 895 mu s and 1.192 ms for digital modulation and channel bandwidth adaptation, respectively. These results show that the adopted design approach is feasible in wireless baseband processing systems. Power estimations suggest that circuit specialization at run-time can potentially improve system power efficiency.

Abstract
Cognitive Radios (CR) are viewed as a solution for spectrum utilization and management in next generation wireless networks. In order to adapt themselves to the actual communications environment, CR devices require highly flexible baseband processing engines. One of the most relevant operations involved in radio baseband processing is the FFT. This work presents a reconfigurable FFT processor supporting FFT sizes and throughputs required by the most used wireless communication standards. By employing Dynamic Partial Reconfiguration (DPR), the implemented design can adapt the FFT size at run-time and specialize its operation to the immediate communication demands. This translates to hardware savings, enhanced resource usage efficiency and possible power savings. The results obtained for reconfiguration times suggest that DPR techniques are a viable option for designing flexible and adaptable baseband processing components for CR devices. © Springer International Publishing Switzerland 2016.

Abstract
The proliferation of new wireless communication technologies and services led to a boost in the number of different available communication standards and spectrum usage. As the electromagnetic spectrum is a finite resource, concerns about its efficient management became an important aspect. Given this scenario, Cognitive Radio emerged as a solution for future wireless communication devices, by supporting multiple standards and improving spectrum utilization through opportunistic wireless access. The purpose of this research is to study and design a reconfigurable FPGA-based NC-OFDM baseband processor meeting the requirements of next generation Cognitive Radio devices in terms of multi-carrier, multi-standard communications and spectral agility in changing environments. The processor will be the core of a flexible NC-OFDM transceiver for future 5G communications with support for spectrum aggregation and run-time selection of modulation schemes and active sub-carriers. The goal is to achieve higher levels of system adaptability, upgradeability and efficiency, by employing dynamic partial reconfiguration of FPGAs.

Abstract
Filter-bank Multicarrier (FBMC) modulation has been proposed as a 5G waveform candidate due to its better spectral efficiency and lower out-of-band emissions compared to OFDM. This paper presents an FPGA-based implementation of a Frequency Spreading FBMC-OQAM baseband modulator and evaluates it in terms of performance, resource utilization and power consumption. The proposed system is then compared with published Polyphase Network (PPN) FBMC-OQAM designs, focusing on resource utilization. The results suggest that the higher computational complexity of FS-FBMC systems does not directly result in higher resource utilization, which makes FS-FBMC a convenient scheme for implementing FBMC designs on FPGA.

Abstract
The usage of application-specific hardware based on Field-Programmable Gate Arrays (FPGA) has proven its benefits. Current system-on-chips, which contain FPGA fabric, supporting dynamic partial reconfiguration, enable a dynamic hardware acceleration for hardware/software co-designs. With the trend to consolidate multiple computing systems into a single system, applications with mixed criticalities can come into conflict. With our approach, we are exploring the possibility to utilize dedicated hardware for the system management and benefit from possible parallelization of applications and system management tasks.