1998
Autores
Delgado, CJM; dos Santos, PL; de Carvalho, JLM;
Publicação
PROCEEDINGS OF THE 37TH IEEE CONFERENCE ON DECISION AND CONTROL, VOLS 1-4
Abstract
A subspace-based on-line identification algorithm based on one specific technique, based on Van Overschee and De Moor's results, but can be adapted to other similar methods since they all recover from the state sequence and the observability matrix is presented. These results relate an estimated Kalman filter sequence with an oblique projection. With further improvements, the algorithm can adapt to the identification of time-variant systems.
1998
Autores
E. R. Almeida, F; M. M. Moura, R;
Publicação
4th EEGS Meeting
Abstract
1998
Autores
Moura, R; E. Oliveira, J; M. Modesto, C; E. Almeida, F; Senos Matias, M;
Publicação
4th EEGS Meeting
Abstract
1998
Autores
Moura, R; Senos Matias, M;
Publicação
4th EEGS Meeting
Abstract
1997
Autores
Alves, JC; Puga, A; CorteReal, L; Matos, JS;
Publicação
1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS
Abstract
Higher-order statistics extend the analysis methods of non-linear systems and non-gaussian signals based on the autocorrelation and power spectrum. The main drawback of their use in real time applications is the high complexity of their estimation due to the large number of arithmetic operations. This paper presents an experimental vector architecture for the estimation of the higher-order moments. The processor's core is a pipelined multiply-accumulate unit that receives four data vectors and computes in parallel the moment taps up to the fourth-order. The design of custom cache memory organization and address generation circuits has led to more than 11 operations per clock cycle. The architecture was modeled and simulated in Verilog and is presently being implemented in XILINX field-programmable gate arrays (FPGAs) and one custom integrated circuit for the multiply-accumulate unit.
1997
Autores
Da Silva, JM; Alves, JC; Matos, JS;
Publicação
IEE Colloquium (Digest)
Abstract
This paper presents experiments carried out with a prototype test chip provided by the IEEE P1149.4 Mixed-Signal Testing Working Group, which explore the architecture of the proposed analogue boundary module to implement simultaneous observation of power supply current and output voltage, towards mixed current/voltage testing of analogue and mixed-signal circuits.
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