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Publicações

Publicações por João Paiva Cardoso

2018

Compiler Phase Ordering as an Orthogonal Approach for Reducing Energy Consumption

Autores
Nobre, R; Reis, L; Cardoso, JMP;

Publicação
CoRR

Abstract

2018

A Preliminary Study on Hyperparameter Configuration for Human Activity Recognition

Autores
Garcia, KD; Carvalho, T; Moreira, JM; Cardoso, JMP; de Carvalho, ACPLF;

Publicação
CoRR

Abstract

2025

HLS to FPGAs: Extending Software Regions Via Transformations and Offloading Functions to the CPU

Autores
Santos, T; Bispo, J; Cardoso, JMP; Hoe, JC;

Publicação
MCSoC

Abstract
On a CPU-FPGA system, C/C++ applications are typically accelerated by offloading specific code regions onto the FPGA using High-level Synthesis (HLS). Although modern FPGAs can implement increasingly large and complex designs, the size and variety of potential offloading code regions remain constrained by the limitations of HLS tools (e.g., no support for dynamic memory allocation and system calls). This paper proposes automated C/C++ source-to-source transformations that tackle these limitations in two steps. Firstly, transformations reduce the entropy of an input C/C++ application by converting it into a subset of C, e.g., by flattening arrays and structs. Secondly, additional transformations make a selected code region synthesizable, e.g., by moving dynamic memory allocations out of the region, converting them to static memory, and offloading non-synthesizable C standard library calls, such as printf(), to the CPU. We evaluate the impact of these transformations showing results obtained through Vitis HLS for four real-world examples: the disparity and texture-synthesis benchmarks from CortexSuite, which contain dynamic memory allocations and indirect pointers in their hotspots; llama2, a Large Language Model that calls printf() every time it predicts a new word; and the spam-filter benchmark from Rosetta, as a debugging showcase. © 2025 IEEE.

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