Abstract
In order for parallel logic programming systems to become popular; they should serve the broadest range of applications. To achieve this goal, designers of parallel logic programming systems would like to exploit maximum parallelism for existing and novel applications. ideally by supporting both and-parallelism and or-parallelism. Unfortunately; the combination of both forms of parallelism is a hard problem, and available proposals cannot match the efficiency of; say, or-parallel only systems. We propose a novel approach to And/Or Parallelism in logic programs. Our initial observation is that stack copying, the most popular technique in or-parallel systems, does not work well with And/Or systems because network management is much more complex. Copying is also a significant problem in operating system where the copy-on-write (COW) has been dcl eloped to address the problem We demonstrate that this technique can also be applied to And/Or systems, and present both shared memory and distributed shared memory designs.

Abstract
In this work we investigate how different machine settings for a hardware Distributed Shared Memory (DSM) architecture affect the performance of parallel logic programming (PLP) systems. We use execution-driven simulation of a DASH-like multiprocessor to study the impact of the cache block size, the cache size, the network bandwidth, the write buffer size, and the coherence protocol on the performance of Andorra-I, a PLP system capable of exploiting implicit parallelism in Prolog programs. Among several other observations, we find that PLP systems favour small cache blocks regardless of the coherence protocol, while they favour large cache sizes only in the case of invalidate-based coherence. We conclude that the cache block size, the cache size, the network bandwidth, and the coherence protocol have a significant impact on the performance, while the size of the write buffer is somewhat irrelevant.

Abstract

Abstract

Abstract
In this work we investigate how Distributed Shared Memory (DSM) architectures affect performance of or-parallel logic programming systems and how this performance approaches that of conventional C systems. Our work concentrates on basic performance, scalability, and programmability. We use execution-driven simulation of a hardware DSM (DASH) to investigate the access patterns and caching behaviour exhibited by parallel C programs and by Aurora, a parallel logic programming system capable of exploiting implicit parallelism in Prolog programs. Aurora was originally written to run on bus-based shared-memory platforms. © Springer-Verlag Berlin Heidelberg 1999.

Abstract
We propose a simple model of distribution for mobile processes, independent of the underlying calculus. Conventional processes compute within sites; inter-site computation is achieved by message sending and object migration, both obeying a lexical scope. We focus on the semantics of networks, on programming practice, and on physical realization with current technology. ©1998 Published by Elsevier Science B.V.