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Byte-code representation has been used to implement several programming languages such as Lisp, ML, Prolog, or Java. In this work, we discuss the impact of several emulator optimisations for the Prolog system YAP YAP obtains performance comparable or exceeding well-known Prolog systems by applying several different styles of optimisations, such as improving the emulation mechanism, exploiting the characteristics of the underlying hardware, and improving the abstract machine itself. We give throughout a detailed performance analysis, demonstrating that low-level optimisations can have a very significant impact on the whole system and across a range of architectures.

Abstract
In order for parallel logic programming systems to become popular; they should serve the broadest range of applications. To achieve this goal, designers of parallel logic programming systems would like to exploit maximum parallelism for existing and novel applications. ideally by supporting both and-parallelism and or-parallelism. Unfortunately; the combination of both forms of parallelism is a hard problem, and available proposals cannot match the efficiency of; say, or-parallel only systems. We propose a novel approach to And/Or Parallelism in logic programs. Our initial observation is that stack copying, the most popular technique in or-parallel systems, does not work well with And/Or systems because network management is much more complex. Copying is also a significant problem in operating system where the copy-on-write (COW) has been dcl eloped to address the problem We demonstrate that this technique can also be applied to And/Or systems, and present both shared memory and distributed shared memory designs.

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In this work we investigate how different machine settings for a hardware Distributed Shared Memory (DSM) architecture affect the performance of parallel logic programming (PLP) systems. We use execution-driven simulation of a DASH-like multiprocessor to study the impact of the cache block size, the cache size, the network bandwidth, the write buffer size, and the coherence protocol on the performance of Andorra-I, a PLP system capable of exploiting implicit parallelism in Prolog programs. Among several other observations, we find that PLP systems favour small cache blocks regardless of the coherence protocol, while they favour large cache sizes only in the case of invalidate-based coherence. We conclude that the cache block size, the cache size, the network bandwidth, and the coherence protocol have a significant impact on the performance, while the size of the write buffer is somewhat irrelevant.

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