Abstract
The work reported in this paper introduces a periodic switching technique applied to continuous-time filters, whose outcome is an equivalent filter with scaled time-constants. The principle behind the method is based on a procedure that extends the integration time by periodically interrupting the normal integration of the filter. The net result is an up scaling of the time constant, inversely proportional to the switching duty-cycle. This is particularly suitable for reducing the area occupied by passive devices in integrated circuits, as well as to accurately calibrate the filter dynamics. Previous works have been following this concept in an entirely continuous-time perspective, either focusing on specific circuits or using approximations to provide an extended analysis. This paper includes input/output sampling to derive a closed-form representation for the scaling technique herein coined as 'Filter & Hold' (F&H). A detailed mathematical analysis is described, demonstrating that the F&H concept represents an exact filtering solution. Simulation results and experimental measurements are provided to further validate the theoretical analysis for an F&H vector-filter prototype. Copyright (C) 2014 John Wiley & Sons, Ltd.

Abstract
This paper presents a wide input range, low-power operational transconductance amplifier (OTA) in weak inversion. The OTA is implemented with tanh-triplets differential pairs, degenerated by a composite configuration to augment the input linear range, thus reducing further the harmonic distortion. Using MATLAB, the mismatch factor (A) of a typical multi-tanh triplet has been optimised for minimum harmonic distortion. The OTA is designed in UMC 0.13um CMOS technology with 1.2V supply. Simulations show that the input range can be extended to 300 mV, while keeping the HD3 below -80 dB. The average power consumption is 13nW, with an open loop-gain of 76 dB and a unity gain frequency of 250 Hz. The low harmonic distortion OTA can find potential applications in low-power and long time constant filters.

Abstract
This paper discusses the possibility of using adaptive signal processing techniques for maximum power point tracking controllers, in order to extract peak power from individual photovoltaic modules. A new technique grounded on unsupervised Hebbian learning theory (maximum eigenvector of the output power) is presented, which works on-online and is capable of operating without a desired response. Important modifications were made to the generic Hebbian adaptation to accommodate the intrinsic feedback loop between the controller and the plant. Analytic derivation of the new update rule is presented, as well as stability analysis by means of Lyapunov theory. Simulation results showing its effectiveness are presented, as well as experimental results.

Abstract
This paper presents analog building blocks that find potential applications in display panels. A buffer (source-follower), subtractor, adder, and high-gain amplifier, employing only n-type enhancement amorphous gallium-indium-zinc-oxide thin-film transistors (a-GIZO TFTs), were designed, simulated, fabricated, and characterized. Circuit simulations were carried out using a neural model developed in-house from the measured characteristics of the transistors. The adder-subtractor circuit presents a power consumption of 0.26 mW, and the amplifier presents a gain of 34 dB and a power consumption of 0.576 mW, with a load of 10 M Omega//16 pF. To the authors' knowledge, this is the highest gain reported so far for a single-stage amplifier with a-GIZO TFT technology.

Abstract
An integrate-and-fire modulator (IFM) is designed for power scavenging systems like: Wireless Sensor Network (WSN) and Radio Frequency Identification (RFID) sensor tags. The circuit works with a clock in order to be able to be synchronized with microprocessors, which must be used to reconstruct the signal. The modulator is simulated using 130nm CMOS technology and the resulting power consumption is around 14nW at a clock frequency of 10 kHz. The OTA individually dissipates roughly 13nW. Signal reconstruction resulted in a 9.2 ENOB.

Abstract
IEEE 1149.1, commonly known as the joint test action group (JTAG), is the standard for the test access port and the boundary-scan architecture. The JTAG is primarily utilized at the time of the integrated circuit (IC) manufacture but also in the field, giving access to internal sub-systems of the IC, or for failure analysis and debugging. Because the JTAG needs to be left intact and operational for use, it inevitably provides a "backdoor" that can be exploited to undermine the security of the chip. Potential attackers can then use the JTAG to dump critical data or reverse engineer IP cores, for example. Since an attacker will use the JTAG differently from a legitimate user, it is possible to detect the difference using machine-learning algorithms. A JTAG protection scheme, SLIC-J, is proposed to monitor user behavior and detect illegitimate accesses to the JTAG. Specifically, JTAG access is characterized using a set of specifically-defined features, and then an on-chip classifier is used to predict whether the user is legitimate or not. To validate the effectiveness of the approach, both legitimate and illegitimate JTAG accesses are simulated using the OpenSPARC T2 benchmark. The results show that the detection accuracy is 99.2%, and the escape rate is 0.8%.