Abstract
This chapter addresses a wearable body area network (BAN) system for both medical and nonmedical applications, especially those including a large number of sensors at BAN scale (<250), embedded in textile and with high data rate (<9+9 MHz) communication demands. The overall system includes an on-body central processing module (CPM) connected to a computer via a wireless link and a wearable sensor network. Due to the fixed location of the sensors and the possibility of using conductive yarns in textiles, a wired network has been considered for the wearable components. Employing conductive yarns instead of using wireless links provides a more reliable communication, higher data rates and throughput, and less power consumption. The wearable unit is composed of two types of circuits, the sensor nodes (SNs) and a base station (BS), all connected to each other with conductive yarns forming a mesh topology with the base node at the center. The reliability analysis shows that communication in a multi-hop connection of sensors in mesh topology is more reliable than in the conventional star topology. From the standpoint of the network, each SN is a four port router capable of handling packets from destination nodes to the BS. The end-to-end communication uses packet switching for packet delivery from SNs to the BS or in the reverse direction, or between SNs. The communication module has been implemented in a low power field programmable gate arrays (FPGA) and a microcontroller. The maximum data rate of the system is 9+9 Mbps while supporting tens of sensors, which is much more than current BAN applications need. The suitability of the proposed system for utilization in real applications has been demonstrated experimentally. © The Institution of Engineering and Technology 2017.

Abstract
Sequential Minimal Optimization (SMO) is the traditional training algorithm for Support Vector Machines (SVMs). However, SMO does not scale well with the size of the training set. For that reason, Stochastic Gradient Descent (SGD) algorithms, which have better scalability, are a better option for massive data mining applications. Furthermore, even with the use of SGD, training times can become extremely large depending on the data set. For this reason, accelerators such as Field-programmable Gate Arrays (FPGAs) are used. This work describes an implementation in hardware, using FPGA, of a fully parallel SVM using Stochastic Gradient Descent. The proposed FPGA implementation of an SVM with SGD presents speedups of more than 10,000x relative to software implementations running on a quad-core processor and up to 319x compared to state-of-the-art FPGA implementations while requiring fewer hardware resources. The results show that the proposed architecture is a viable solution for highly demanding problems such as those present in big data analysis.

Abstract

Abstract
Automatic speaker identification typically relies on sophisticated statistical modeling and classification which requires large amounts of data for good performance. However, in actual audio forensics casework, frequently only a few seconds of speech material are available. In this paper, we favor diversity in feature extraction, simple modeling and classification, and constructive combination of congruent classification scores. We use phase, spectral magnitude and F0-related features in speaker identification experiments on a database of 35 speakers most of whom are twins. Using only 4.4 sec. of vowel-like sounds per speaker, we characterize the performance that is reached with individual features and we characterize simple and yet effective ways of classification score fusion. Insights for further research are also presented.

Abstract
In IEEE 802.11 based wireless networks interference increases as more access points are added. A metric helping to quantize this interference seems to be of high interest. In this paper we study the relationship between the improved attacking case metric, which captures interference, and throughput for IEEE 802.11 based network using directional antenna. The y(1/3) = a + b (ln x)(3) model was found to best represent the relationship between the interference metric and the network throughput. We use this model to predict the performance of similar networks and decide the best configuration a network operator could use for planning his network.

Abstract
A common problem in networking research and development is the duplicate effort of writing simulation and implementation code of routing protocols. This can be avoided by reusing simulation code in real prototyping and in production environments. In ns-3, emulation mode can be used to run simulation models of routing and Software Defined Networking (SDN) protocols on top of real L2 interfaces such as Ethernet and Wi-Fi. Although this feature is already available, the additional packet processing involved degrades the performance of the nodes and limits the amount of network traffic that can be processed. Our proposal to overcome this performance bottleneck consists in moving the data plane processing operations to outside of the ns-3 process, running such operations natively in the host Operating System (OS). Two approaches are proposed: (a) running the data plane in user space (DPU); (b) running the data plane in kernel space (DPK). Both approaches support the emulation of one or multiple nodes per emulation host machine. The experimental results show that the DPU and DPK approaches significantly improve the throughput by respectively 4.9 and 19 times when compared against traditional ns-3 emulation of a single node. For multiple nodes, the DPK approach further improves the throughput by as much as 23 times. The amount of code reuse is high - e.g., for the routing protocols used in this paper, only 1.4% and 11% of extra code is required to benefit from the performance improvements achieved respectively by the DPK and DPU approaches.