Abstract

Abstract
Rhythmic similarity, a fundamental task within Music Information Retrieval, has recently been applied in creative music contexts to retrieve musical audio or guide audio-content transformations. However, there is still very little knowledge of the typical rhythmic similarity values between overlapping musical structures per instrument, genre, and time scales, which we denote as rhythmic compatibility. This research provides the first steps towards the understanding of rhythmic compatibility from the systematic analysis of MedleyDB, a large multi-track musical database composed and performed by artists. We apply computational methods to compare database stems using representative rhythmic similarity metrics - Rhythmic Histogram (RH) and Beat Spectrum (BS) - per genre and instrumental families and to understand whether RH and BS are prone to discriminate genres at different time scales. Our results suggest that 1) rhythmic compatibility values lie between [.002,.354] (RH) and [.1,.881] (BS), 2) RH outperforms BS in discriminating genres, and 3) different time scale in RH and BS impose significant differences in rhythmic compatibility. © 2021 ACM.

Abstract

Abstract
The recent Bluetooth 5.1 specification introduced the use of Angle-of-Arrival (AoA) information which enables the design of novel low-cost indoor positioning systems. Existing approaches rely on multiple fixed gateways equipped with antenna arrays, in order to determine the location of an arbitrary number of simple mobile omni-directional emitters. In this paper, we instead present an approach where mobile receivers are equipped with antenna arrays, and the fixed infrastructure is composed of battery-powered beacons. We implement a simulator to evaluate the solution using a real-world data set of AoA measurements. We evaluated the solution as a function of the number of beacons, their transmission period, and algorithmic parameters of the position estimation. Sub-meter accuracy is achievable using 1 beacon per 15 m(2) and a beacon transmission period of 500 ms.

Abstract
We discuss the concept of FPGA-unfriendliness, the property of certain algorithms, programs, or domains which may limit their applicability to FPGAs. Specifically, we look at graph analysis, which has recently seen increased interest in combination with High-Level Synthesis, but has yet to find great success compared to established acceleration mechanisms. To this end, we make use of Xilinx's Vitis Graph Library to implement Single-Source Shortest Paths (SSSP) and PageRank (PR), and present a custom kernel written from the ground up for Distinctiveness Centrality (DC, a novel graph centrality measure). We use public datasets to test these implementations, and analyse power consumption and execution time. Our comparisons against published data for GPU and CPU execution show FPGA slowdowns in execution time between around 18.5x and 328x for SSSP, and around 1.8x and 195x for PR, respectively. In some instances, we obtained FPGA speedups versus CPU of up to 2.5x for PR. Regarding DC, results show speedups from 0.1x to 3.5x, and energy efficiency increases from 0.8x to 6x. Lastly, we provide some insights regarding the applicability of FPGAs in FPGA-unfriendly domains, and comment on the future as FPGA and HLS technology advances.

Abstract