Abstract
Driving simulators are essential tools for training, education, research, and scientific experimentation. However, the diversity and quality of virtual environments in simulations is limited by the specialized human resources availability for authoring the content, leading to repetitive scenarios and low complexity of real-world scenes. This work introduces a pipeline that can process text-based narratives outlining driving experiments to procedurally generate dynamic traffic simulation scenarios. The solution uses Retrieval-Augmented Generation alongside local open-source Large Language Models to analyse unstructured textual information and produce a knowledge graph that encapsulates the world scene described in the experiment. Additionally, a context-based formal grammar is generated through inverse procedural modelling, reflecting the game mechanics related to the interactions among the world entities in the virtual environment supported by CARLA driving simulator. The proposed pipeline aims to simplify the generation of virtual environments for traffic simulation based on descriptions from scientific experiment, even for users without expertise in computer graphics. © 2025 by SCITEPRESS–Science and Technology Publications, Lda.

Abstract
The virtual reconstitution of Castelo de Vide, Portugal, within the FRONTOWNS project, highlights the challenges and successes of multidisciplinary collaboration in heritage preservation through 3D modeling. The goal was to reconstruct the town's urban evolution, focusing on its role as a border settlement from the 13th to 16th centuries. The project combined archaeological evidence, historical sources, and digital technologies like photogrammetry and 3D scanning. Co-creation workshops aligned diverse knowledge, leading to creative solutions that balanced historical accuracy and technical feasibility. Despite budget constraints, it produced a high-quality digital reconstitution with insights for future virtual heritage projects.

Abstract
Traditional approaches in the competitive recruitment landscape frequently encounter difficulties in effectively identifying exceptional applicants, resulting in delays, increased expenses, and biases. This study proposes the utilisation of contemporary technologies such as Large Language Models (LLMs) and chatbots to automate the process of resume screening, thereby diminishing prejudices and enhancing communication between recruiters and candidates. Algorithms based on LLM can greatly transform the process of screening by improving both its speed and accuracy. By integrating chatbots, it becomes possible to have personalised interactions with candidates and streamline the process of scheduling interviews. This strategy accelerates the hiring process while maintaining principles of justice and ethics. Its objective is to improve algorithms and procedures to meet changing requirements and enhance the competitive advantage of talent acquisition within organisations.

Abstract
The International Symposium on Applied Reconfigurable Computing (ARC) is an annual forum for the discussion and dissemination of research, notably applying the Reconfigurable Computing (RC) concept to real-world problems. The first edition of ARC took place in 2005, and in 2024, ARC celebrated its 20th edition. During those 20 years, the field of reconfigurable computing saw a tremendous growth in its underlying technology. ARC contributed very significantly to the presentation and dissemination of new ideas, innovative applications, and fruitful discussions, all of which have resulted in the shaping of novel lines of research. Here, we present selected papers from the first 20 years of ARC, that we believe represent the corpus of work and reflect the ARC spirit by covering a broad spectrum of RC applications, benchmarks, tools, and architectures. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

Abstract
Heterogeneous CPU-FPGA C/C++ applications may rely on High-level Synthesis (HLS) tools to generate hardware for critical code regions. As typical HLS tools have several restrictions in terms of supported language features, to increase the size and variety of offloaded regions, we propose several code transformations to improve synthesizability. Such code transformations include: struct and array flattening; moving dynamic memory allocations out of a region; transforming dynamic memory allocations into static; and asynchronously executing host functions, e.g., printf(). We evaluate the impact of these transformations on code region size using three real-world applications whose critical regions are limited by non-synthesizable C/C++ language features. © 2025 IEEE.

Abstract
Critical performance regions of software applications are often accelerated by offloading them onto an FPGA. An efficient end result requires the judicious application of two processes: hardware/software (hw/sw) partitioning, which identifies the regions for offloading, and the optimization of those regions for efficient High-level Synthesis (HLS). Both processes are commonly applied separately, not relying on any potential interplay between them, and not revealing how the decisions made in one process could positively influence the other. This paper describes our primary efforts and contributions made so far, and our work-in-progress, in an approach that combines both hw/sw partitioning and optimization into a unified, holistic process, automated using source-to-source compilation. By using an Extended Task Graph (ETG) representation of a C/C++ application, and expanding the synthesizable code regions, our approach aims at creating clusters of tasks for offloading by a) maximizing the potential optimizations applied to the cluster, b) minimizing the global communication cost, and c) grouping tasks that share data in the same cluster. © 2025 IEEE.