Abstract
The REFLECT project aimed at developing, validating, and evaluating a novel compilation and synthesis approach for heterogeneous multi-core computing systems that relies on aspect-oriented specifications to convey critical domain knowledge to all design/development stages of an integrated toolchain. To reach these goals, we have devised a new compilation and synthesis foundation combining distinct but synergistic areas of research, namely, aspect-oriented programming, hardware compilation, design patterns, and hardware templates. © Springer Science+Business Media New York 2013. All rights are reserved.

Abstract
A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration for every mode separately. To switch between modes the complete reconfigurable region is rewritten, which often leads to very long reconfiguration times. In this paper we present a novel, fully automated tool flow that exploits similarities between the modes and uses Dynamic Circuit Specialization to drastically reduce reconfiguration time. Experimental results show that the number of bits that is rewritten in the configuration memory reduces with a factor from 4.6× to 5.1× without significant performance penalties. © 2013 EDAA.

Abstract
This chapter describes the CoSy1-based [1, 2] compilers developed in the context of the REFLECT project to support its aspect-oriented design-flow. In particular, these CoSy-based compilers are guided by LARA strategies and are responsible for generating code targeting traditional processors, as well as generating behavioral-RTL VHDL code [3] targeting hardware accelerators. Throughout this chapter, these compilers are referred collectively as reflectc, except when a specific compilation flow (with its specific name) is used. We also describe the compiler development extensions to support the REFLECT approach [4] and the weaving process controlled by LARA strategies [5-7] as described in Chap. 3. © Springer Science+Business Media New York 2013. All rights are reserved.

Abstract

Abstract
This chapter presents the most relevant related work with respect to the compilation and synthesis approach developed in the context of the REFLECT project. We survey current techniques and methodologies for the mapping of computations described in high-level programming languages to reconfigurable architectures. We give particular emphasis to compilation systems that map imperative (C-like) languages to target FPGA-based systems. We also describe previous work on compiler optimizations, automated high-level synthesis, and strategies for back-end synthesis, mapping as well as placement and routing. Finally, we include an overview of EU-funded projects relevant to REFLECT. © Springer Science+Business Media New York 2013. All rights are reserved.

Abstract
Source-to-source weaving is a key mechanism in the REFLECT design-flow since it allows the inclusion of application-specific information in the transformed program. In particular, LARA [1, 2] aspects are used to control the design-flow, and to trigger source-to-source code transformations and compilation/synthesis optimizations on a given application. Hence, user knowledge about an application and/or target architecture can be codified as aspects, allowing the original application code to be automatically extended to satisfy non-functional concerns, such as arithmetic precision and performance. © Springer Science+Business Media New York 2013. All rights are reserved.