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Detalhes

Detalhes

  • Nome

    João Bispo
  • Cluster

    Informática
  • Cargo

    Responsável de Área
  • Desde

    01 maio 2015
Publicações

2021

A Binary Translation Framework for Automated Hardware Generation

Autores
Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP;

Publicação
IEEE Micro

Abstract

2020

Source-to-source compilation targeting OpenMP-based automatic parallelization of C applications

Autores
Arabnejad, H; Bispo, J; Cardoso, JMP; Barbosa, JG;

Publicação
Journal of Supercomputing

Abstract
Directive-driven programming models, such as OpenMP, are one solution for exploring the potential parallelism when targeting multicore architectures. Although these approaches significantly help developers, code parallelization is still a non-trivial and time-consuming process, requiring parallel programming skills. Thus, many efforts have been made toward automatic parallelization of the existing sequential code. This article presents AutoPar-Clava, an OpenMP-based automatic parallelization compiler which: (1) statically detects parallelizable loops in C applications; (2) classifies variables used inside the target loop based on their access pattern; (3) supports reduction clauses on scalar and array variables whenever it is applicable; and (4) generates a C OpenMP parallel code from the input sequential version. The effectiveness of AutoPar-Clava is evaluated by using the NAS and Polyhedral Benchmark suites and targeting a x86-based computing platform. The achieved results are very promising and compare favorably with closely related auto-parallelization compilers, such as Intel C/C++ Compiler (icc), ROSE, TRACO and CETUS. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

2020

Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture

Autores
de Souza, CAO; Bispo, J; Cardoso, JMP; Diniz, PC; Marques, E;

Publicação
ELECTRONICS

Abstract
In this article, we focus on the acceleration of a chemical reaction simulation that relies on a system of stiff ordinary differential equation (ODEs) targeting heterogeneous computing systems with CPUs and field-programmable gate arrays (FPGAs). Specifically, we target an essential kernel of the coupled chemistry aerosol-tracer transport model to the Brazilian developments on the regional atmospheric modeling system (CCATT-BRAMS). We focus on a linear solve step using the QR factorization based on the modified Gram-Schmidt method as the basis of the ODE solver in this application. We target Intel hardware accelerator research program (HARP) architecture with the OpenCL programming environment for these early experiments. Our design exploration reveals a hardware design that is up to 4 times faster than the original iterative Jacobi method used in this solver. Still, even with hardware support, the overall performance of our QR-based hardware is lower than its original software version.

2020

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework

Autores
Paulino, N; Ferreira, JC; Bispo, J; Cardoso, JMP;

Publicação
30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020

Abstract

2020

Clava: C/C plus plus source-to-source compilation using LARA

Autores
Bispo, J; Cardoso, JMP;

Publicação
SOFTWAREX

Abstract
This article presents Clava, a Clang-based source-to-source compiler, that accepts scripts written in LARA, a JavaScript-based DSL with special constructs for code queries, analysis and transformations. Clava improves Clang's source-to-source capabilities by providing a more convenient and flexible way to analyze, transform and generate C/C++ code, and provides support for building strategies that capture run-time behavior. We present the Clava framework, its main capabilities, and how it can been used. Furthermore, we show that Clava is sufficiently robust to analyze, instrument and test a set of large C/C++ application codes, such as GCC. (C) 2020 The Authors. Published by Elsevier B.V.

Teses
supervisionadas

2020

Recommendation Engine for Parallel Loops

Autor
José Luís Oliveira da Cunha

Instituição
UP-FEUP

2020

An Exploration of FPGAs as Accelerators for Graph Analysis via High-Level Synthesis

Autor
Pedro Filipe Vilhena de Campos Oliveira e Silva

Instituição
UP-FEUP

2020

Generating Hardware Modules via Binary Translation of RISC-V Binaries

Autor
João Miguel Curado Conceição

Instituição
UP-FEUP

2020

Restructuring C code for High-Level Synthesis Targeting FPGAs

Autor
Renato Alexandre Sousa Campos

Instituição
UP-FEUP

2020

Acceleration of Applications with FPGA-based Computing Machines: Code Restructuring

Autor
Tiago Lascasas dos Santos

Instituição
UP-FEUP