2019
Authors
Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; Cmar, R; Cardoso, JMP; Cavazzoni, C; Cesarini, D; Cherubin, S; Ficarelli, F; Gadioli, D; Golasowski, M; Libri, A; Martinovic, J; Palermo, G; Pinto, P; Rohou, E; Slaninová, K; Vitali, E;
Publication
MICROPROCESSORS AND MICROSYSTEMS
Abstract
The ANTAREX project relies on a Domain Specific Language (DSL) based on Aspect Oriented Programming (AOP) concepts to allow applications to enforce extra functional properties such as energy-efficiency and performance and to optimize Quality of Service (QoS) in an adaptive way. The DSL approach allows the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management. In this paper, we present an overview of the key outcome of the project, the ANTAREX DSL, and some of its capabilities through a number of examples, including how the DSL is applied in the context of the project use cases.
2025
Authors
Gallego, J; Ferreira, JP; Alves, L; Vázquez, D; Bispo, J; Rodríguez, A; Paulino, N; Otero, A;
Publication
DCIS
Abstract
Executing Artificial Intelligence (AI) at the edge is challenging due to tight energy and computational constraints. Heterogeneous platforms, particularly those incorporating Coarse-Grained Reconfigurable Arrays (CGRAs), offer a compelling trade-off between hardware specialization and programmability, supporting spatially distributed and energyefficient computation. Despite their potential, the deployment of applications on CGRA accelerators remains limited by the lack of practical toolchains and methodologies. In this work, we propose a compilation flow based on MLIR to enable the seamless integration of both C/C++ kernels and ONNX-based AI models into a RISC-V system augmented with a CGRA accelerator. Our approach extracts the underlying Data Flow Graph (DFG) from the high-level representation. It maps it onto the CGRA using an Integer Linear Programming (ILP) mapper that accounts for the accelerator's architectural constraints. A custom backend completes the toolchain by generating the necessary binaries for coordinated execution across the RISC-V processor and the CGRA. This framework enables the practical deployment of heterogeneous edge workloads, combining the flexibility of software execution with the efficiency of hardware acceleration. © 2025 IEEE.
2025
Authors
Santos, T; Bispo, J; Cardoso, JMP; Hoe, JC;
Publication
MCSoC
Abstract
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