Abstract
Executing Artificial Intelligence (AI) at the edge is challenging due to tight energy and computational constraints. Heterogeneous platforms, particularly those incorporating Coarse-Grained Reconfigurable Arrays (CGRAs), offer a compelling trade-off between hardware specialization and programmability, supporting spatially distributed and energyefficient computation. Despite their potential, the deployment of applications on CGRA accelerators remains limited by the lack of practical toolchains and methodologies. In this work, we propose a compilation flow based on MLIR to enable the seamless integration of both C/C++ kernels and ONNX-based AI models into a RISC-V system augmented with a CGRA accelerator. Our approach extracts the underlying Data Flow Graph (DFG) from the high-level representation. It maps it onto the CGRA using an Integer Linear Programming (ILP) mapper that accounts for the accelerator's architectural constraints. A custom backend completes the toolchain by generating the necessary binaries for coordinated execution across the RISC-V processor and the CGRA. This framework enables the practical deployment of heterogeneous edge workloads, combining the flexibility of software execution with the efficiency of hardware acceleration. © 2025 IEEE.