Abstract
Advancements in semiconductor technology no longer occur at the pace the industry had been accustomed to. We have entered what is considered by many to be the post-Moore era. In order to continue scaling performance, increasingly heterogeneous architectures are being developed and the use of special purpose accelerators is on the rise. One notable example are Field-Programmable-Gate-Arrays (FPGAs), both in the data-center and embedded spaces. Advances in FPGA features and tools is allowing for critical kernels to be accelerated on specialized hardware without fabrication costs. However, re-targeting code to such heterogeneous platforms still requires significant refactoring of the compute intensive kernels, as well as knowledge of parallel compute and hardware design concepts for maximization of performance. We present Tribble, a source-to-source framework under active development, capable of transforming regular C/C++ programs for execution on heterogeneous architectures. This includes transforming the target kernel source code so that it is amenable for circuit generation while keeping the original version for software execution, inserting code for task and memory management and injecting a scheduler algorithm.

Abstract

Abstract
This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9x and 18.2x for a Micro Blaze CPU without cache. We estimate speedups from 1.03x to 2.01x, when comparing to the best estimated performance achieved with a single Micro Blaze. © 2011 IEEE.

Abstract
Deep learning methods have been shown to be competitive solutions for modulation classification tasks, but suffer from being computationally expensive, limiting their use on embedded devices. We propose a new deep neural network architecture which employs known structures, depth-wise separable convolution and residual connections, as well as a compression methodology, which combined lead to a tiny and fast algorithm for modulation classification. Our compressed model won the first place in ITU's AI/ML in 5G Challenge 2021, achieving 61.73? compression over the challenge baseline and being over 2.6? better than the second best submission. The source code of this work is publicly available at github.com/ITU-AI- ML-in-5G-Challenge/ITU-ML5G-PS-007-BacalhauNet.

Abstract

Abstract