Cookies Policy
The website need some cookies and similar means to function. If you permit us, we will use those means to collect data on your visits for aggregated statistics to improve our service. Find out More
Accept Reject
  • Menu
Publications

Publications by João Paiva Cardoso

2012

Analysis of error detection schemes: Toolchain support and hardware/software implications

Authors
Azarian, A; Ferreira, JC; Werner, S; Petrov, Z; Cardoso, JMP; Hübner, M;

Publication
2012 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2012, Erlangen, Germany, June 25-28, 2012

Abstract
Meeting safety requirements typically require substantial invasive extensions to applications. Even in the absence of faults, the overhead associated with these invasive extensions may unacceptably increase execution time. In this paper we focus on a number of experiments with schemes for error detection, having a 3D Path Planning application for an avionics system as case study. We analyze how these error detection schemes can be implemented to meeting system's time budget. The experiments allowed us to acquire the requirements for automating the application of the error detection schemes in the context of a hardware/software design-flow, and to determine how those schemes can be addressed using a novel approach where safety requirements are described using an aspect- and strategy-oriented programming language, named LARA. For our experiments and validation, we consider an FPGA-based embedded system consisting of a general purpose processor (GPP) coupled to custom computing units which are primarily used for hardware acceleration and for implementing fault detection schemes. © 2012 IEEE.

2012

Specifying Compiler Strategies for FPGA-based Systems

Authors
Cardoso, JMP; Teixeira, J; Alves, JC; Nobre, R; Diniz, PC; Coutinho, JGF; Luk, W;

Publication
2012 IEEE 20TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM)

Abstract
The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is a long and error-prone process. Typically, developers need to be deeply involved in all the stages of the translation and optimization of an application described in a high-level programming language to a lower-level design description to ensure the solution meets the required functionality and performance. This paper describes the use of a novel aspect-oriented hardware/software design approach for FPGA-based embedded platforms. The design-flow uses LARA, a domain-specific aspect-oriented programming language designed to capture high-level specifications of compilation and mapping strategies, including sequences of data/computation transformations and optimizations. With LARA, developers are able to guide a design-flow to partition and map an application between hardware and software components. We illustrate the use of LARA on two complex real-life applications using high-level compilation and synthesis strategies for achieving complete hardware/software implementations with speedups of 2.5x and 6.8x over software-only implementations. By allowing developers to maintain a single application source code, this approach promotes developer productivity as well as code and performance portability.

2016

Message from general and program co-chairs

Authors
Silvano, C; Cardoso, JMP; Agosta, G; Huebner, M;

Publication
ACM International Conference Proceeding Series

Abstract

2021

An Efficient Monte Carlo-Based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System

Authors
Vitali, E; Gadioli, D; Palermo, G; Golasowski, M; Bispo, J; Pinto, P; Martinovic, J; Slaninova, K; Cardoso, JMP; Silvano, C;

Publication
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING

Abstract
Incorporating speed probability distribution to the computation of the route planning in car navigation systems guarantees more accurate and precise responses. In this paper, we propose a novel approach for selecting dynamically the number of samples used for the Monte Carlo simulation to solve the Probabilistic Time-Dependent Routing (PTDR) problem, thus improving the computation efficiency. The proposed method is used to determine in a proactive manner the number of simulations to be done to extract the travel-time estimation for each specific request, while respecting an error threshold as output quality level. The methodology requires a reduced effort on the application development side. We adopted an aspect-oriented programming language (LARA) together with a flexible dynamic autotuning library (mARGOt) respectively to instrument the code and to make decisions on tuning the number of samples to improve the execution efficiency. Experimental results demonstrate that the proposed adaptive approach saves a large fraction of simulations (between 36 and 81 percent) with respect to a static approach, while considering different traffic situations, paths and error requirements. Given the negligible runtime overhead of the proposed approach, the execution-time speedup is between 1.5x and 5.1x. This speedup is reflected at the infrastructure-level in terms of a reduction of 36 percent of the computing resources needed to support the whole navigation pipeline.

2019

The ANTAREX domain specific language for high performance computing

Authors
Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; Cmar, R; Cardoso, JMP; Cavazzoni, C; Cesarini, D; Cherubin, S; Ficarelli, F; Gadioli, D; Golasowski, M; Libri, A; Martinovic, J; Palermo, G; Pinto, P; Rohou, E; Slaninova, K; Vitali, E;

Publication
MICROPROCESSORS AND MICROSYSTEMS

Abstract
The ANTAREX project relies on a Domain Specific Language (DSL) based on Aspect Oriented Programming (AOP) concepts to allow applications to enforce extra functional properties such as energy-efficiency and performance and to optimize Quality of Service (QoS) in an adaptive way. The DSL approach allows the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management. In this paper, we present an overview of the key outcome of the project, the ANTAREX DSL, and some of its capabilities through a number of examples, including how the DSL is applied in the context of the project use cases.

2018

Improving OpenCL Performance by Specializing Compiler Phase Selection and Ordering

Authors
Nobre, R; Reis, L; Cardoso, JMP;

Publication
CoRR

Abstract

  • 44
  • 45