Abstract
Conventional power distribution networks (PDNs), in which individual voltage regulators power the entire integrated circuit (IC), are ineffective for high-power, large-area ICs. In highperformance systems-on-chip (SoCs) and microprocessors (in particular those designed for AI applications), shrinking technology nodes are leading to higher current densities, which impose thermal constraints and limit the portion of the chip that can be simultaneously powered (“dark silicon”). PDNs with point-of-load regulation offer a promising alternative. The distributed nature of their design inherently relaxes thermal constraints while minimizing high-current routing overhead (IR drops), thereby improving the PDN efficiency. In this work, the concept of on-chip distributed voltage regulation is introduced. Previously reported distributed voltage regulator designs are reviewed, emphasizing their major achievements and limitations. Then, the challenges that hinder a more ubiquitous adoption of such designs, namely stability (analysis) and unbalanced load sharing, are discussed. Existing solutions addressing these challenges are also presented. Finally, a comparative analysis of the performance of these regulators is presented, and insights into the future direction of distributed voltage regulation are offered. © (2025), (Universidade do Porto - Faculdade de Engenharia). All rights reserved.

Abstract

Abstract
The increasing use of wearable electronics calls for sustainable energy solutions. Biomechanical energy harvesting appears as an attractive solution to replace the use of batteries in wearables, as the body generates sufficient power to drive small electronics. In particular, triboelectric nanogenerators (TENGs) have emerged as a promising approach due to its lightweight and high power density. In this work, a TENG is hybridized with an electromagnetic generator (EMG) to harvest energy from the foot strike. An enclosed radial-flow turbine is optimized and used to convert the foot-strike low-frequency linear movement into a higher-frequency rotational motion (by a factor of & AP;12). Besides increasing the motion frequency, the employed mechanism is physically robust and enables a continuous operation from irregular mechanical excitations. A single TENG unit operating in the freestanding mode generated an optimal power of 4.72 & mu;W and transferred a short-circuit charge of 2.3 nC. The TENG+EMG hybridization allows to power a digital pedometer even after the mechanical input stopped. Finally, the energy harvester is incorporated into a commercial shoe to power the same pedometer from foot walking. The obtained results validate the developed prototype ability to serve as a portable power source that can drive sensors and wearable electronics.

Abstract
This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.

Abstract
This paper presents two initiatives run by groups of engineering students at the University of Porto: the Microelectronics Students' Group and BioStar. These groups are student-led initiatives that promote different scientific fields through self-guided projects. Both experiences have proven to be very successful in increasing the undergraduate student's interest in science and technology. This work reports the activities, organization and main methodologies employed by these groups, which can be seen as successful approaches to enhance the technical curriculum of students. © 2012 IEEE.

Abstract
This paper presents the results of a preliminary study to examine the ability of post-silicon devices for analog processing. It is focused on the latest thin-film transistors (TFTs) with amorphous gallium-indium-zinc oxide (a-GIZO) as active layer. Three circuit configurations are presented: a differential pair and two multiplier topologies. Both triode and saturation regions of operation are included in the analysis, with the devices set to remain in strong accumulation. A neural model, which is developed based on the measured data of the TFTs, is used for the circuit simulations in the Cadence Virtuoso environment. The analog multipliers simulation results are compared against the expected functional results.