Abstract
This work presents the design and analysis of a biological signal processing accelerator, including an interface controller and memory subsystem for a low-power CGRA. The controller design supports several operation modes, which can perform several applications when paired with the CGRA reconfiguration capabilities. Physical synthesis shows that the controller introduces only a 6 percent area and power overhead compared to the CGRA core, while allowing independent processing of inner loops at high frequencies and the exploitation of pipelining and parallelism. In-depth power analysis based on layout information was performed, including an evaluation of the use of power gating techniques. A practical case study (ECG signal processing) was also evaluated.

Abstract
The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.

Abstract
The use of specialized accelerator circuits is a feasible solution to address performance and energy issues in embedded systems. This paper extends a previous field-programmable gate array-based approach that automatically generates pipelined customized loop accelerators (CLAs) from runtime instruction traces. Despite efficient acceleration, the approach suffered from high area and resource requirements when offloading a large number of kernels from the target application. This paper addresses this by enhancing the CLA with dynamic partial reconfiguration (DPR) support. Each kernel to accelerate is implemented as a variant of a reconfigurable area of the CLA which hosts all functional units and configuration memory. Evaluation of the proposed system is performed on a Virtex-7 device. We show, for a set of 21 kernels, that when comparing two CLAs capable of accelerating the same subset of kernels, the one which benefits from DPR can be up to 4.3x smaller. Resorting to DPR allows for the implementation of CLAs which support numerous kernels without a significant decrease in operating frequency and does not affect the initiation intervals at which kernels are scheduled. Finally, the area required by a CLA instance can be further reduced by increasing the IIs of the scheduled kernels.

Abstract
Source routing (SR) minimum cost forwarding (MCF) – SRMCF – is a reactive, energy-efficient routing protocol proposed to improve the existent MCF methods utilized in heterogeneous wireless sensor networks (WSN). This paper presents an analytical analysis with experimental support that demonstrates the effectiveness of the proposed protocol. SRMCF stems from SR concepts and MCF methods exploited in ad hoc WSNs, where all unicast communications (between sensor nodes and the base station, or vice versa) use minimum cost paths. The protocol utilized in the present work was updated and now also handles link and node failures. Theoretical analysis and simulations show that the final protocol exhibits better throughput and energy consumption than MCF. Memory requirements for the routing table in the base station are also analyzed. Experimental results in a real scenario were obtained for implementations of both protocols, MCF and SRMCF, deployed in a small network of TelosB motes. Results show that SRMCF presents a 33% higher throughput and 24% less energy consumption than MCF. Extensive © 2019 River Publishers

Abstract
A new wearable data capture system for gait analysis is being developed. It consists of a pantyhose with embedded conductive yarns interconnecting customized sensing electronic devices that capture inertial and electromyographic signals and send aggregated information to a personal computer through a wireless link. The use of conductive yarns to build the myoelectric electrodes and the interconnections of the wired sensors network as well as the topology and functionality of the sensor modules are presented. © The Institution of Engineering and Technology 2017.

Abstract
This chapter presents a one-way method for synchronization at the media access control (MAC) layer of nodes and a circuit based on that in a wearable sensor network. The proposed approach minimizes the time skew with an accuracy of half of clock cycle in average. The work is intended to be used in a router integrated circuit (IC) designed for wearable systems. In particular, we address the need for good time synchronization in the simultaneous acquisition of surface electromyographic signals of several muscles. In our main application case, the electrodes are embedded in patient clothes connected to sensor nodes (SNs) equipped with analog-to-digital converters. The SNs are connected together in a network using conducting yarns embedded in the clothes. In the context of such wearable sensor networks, the main contributions of this work are the evaluation of existing protocols for synchronization, the description of a simpler, resource-efficient synchronization protocol, and its analysis, including the determination of the average local and global clock skew and of the synchronization probability in the presence of link failures. Both theoretical analysis and experimental results, in wired wearable networks, show that the proposed protocol has a better performance than precision time protocol (PTP), a standard timing protocol for both single and multihop situations. The proposed approach is simpler, requires no calculations, and exchanges fewer messages. Experimental results obtained with an implementation of the protocol in 0.35 µm complementary metal oxide semiconductor (CMOS) technology show that this approach keeps the one-hop average clock skew around 4.6 ns and peak-to-peak skew around 50 ns for a system clock frequency of 20 MHz. © The Institution of Engineering and Technology 2017.