Abstract
Non-rectangular cores of standard-cell-based reconfigurable logic can be used to fill space left on System-on-Chips, thereby providing the system with hardware reconfigurability. The proposed architecture for a non-rectangular reconfigurable core is based on a fixed set of blocks that implement logic functions, interconnections and configurable switching. The basic blocks connect by abutment to form clusters and clusters abut to form a complete reconfigurable core. A software tool was created to generate a gate-level netlist and the floorplan data of the reconfigurable logic core together with a basic testbench. Cores with non-rectangular shapes were created using 90 nm and 45 nm standard-cell technologies and validated by simulation. The results demonstrate the feasibility of a flexible, technology-independent architecture for non-rectangular reconfigurable logic cores that can be physically implemented using a standard digital design flow.

Abstract
The increasing complexity of mixed-signal boards makes an integrated analogue/digital testability approach an attractive proposition. This paper investigates one such approach based on the use of mixed-signal test support ICs together with standard board level test infrastructures. The architecture of a test support IC and preliminary experimental results are also presented.

Abstract
The paper discusses the need of a test infrastructure to support the testing of mixed-signal electronic systems, and discusses a general architecture for test support ICs that can be used to build it. An implementation of a subset of this architecture is described together with its application in a practical example.

Abstract

Abstract
The Erlang programming language is a concurrency oriented functional language, based on the notion of independent processes and uses message passing for communication between processes. It is specially adapted to the realization of highly reliable distributed systems. In this paper it is analyzed the use of the Erlang's computational paradigm for the design and implementation of application specific heterogeneous computational systems. The main objective is to use for the low level implementation the same computational model used in high level view of the system. This will allow an easier and faster design space exploration and optimization. © 2010 IEEE.

Abstract
Cellular Genetic Algorithms (cGAs) exhibit a natural parallelism that makes them interesting candidates for hardware implementation, as several processing elements can operate simultaneously on subpopulations shared among them. This paper presents a scalable architecture for a cGA, suitable for FPGA implementation. A regular array of custom designed processing elements (PEs) works on a population of solutions that is spread into dual-port memory blocks locally shared by adjacent PEs. A travelling salesman problem with 150 cities was used to verify the implementation of the proposed cGA on a Virtex-6 FPGA, using a population of 128 solutions with different levels of parallelism (1, 4, 16 and 64 PEs). Results have shown that an increase of the number of PEs does not degrade the quality of the convergence of the iterative process, and that the throughput increases almost linearly with the number of PEs. Comparing with a software implementation running in a PC, the cGA with 64 PEs has shown a 45x speedup.