Abstract
Adaptive embedded systems can achieve enhanced flexibility by performing run-time reconfiguration of hardware. This paper describes a method to generate at run-time new partial FPGA configurations corresponding to arithmetic expressions. This is achieved by merging available partial bitstreams of arithmetic components to produce a new partial bitstream for a specific FPGA area. The connections among the components are mapped to the switch matrices of the reconfigurable fabric, and the corresponding information is added to the new partial configuration. The proposed method was implemented for a Virtex-II Pro FPGA with a 300 MHz PowerPC 405 CPU. It was used to create partial configurations in less than 69 s for sets of arithmetic circuits with up to 25 components and 208 connections.

Abstract
A new wearable data capture system for gait analysis is being developed. It consists of a pantyhose with embedded conductive yarns interconnecting customized sensing electronic devices that capture inertial and electromyographic signals and sends aggregated information to a personal computer through a wireless link. The use of conductive yarns to build the myoelectric electrodes and the interconnections of the wired sensors network, as well as the topology and functionality of the sensor modules are presented.

Abstract
This paper presents a network circuit for wearable low-power BAN (Body Area Networks) applications, geared towards mesh network topologies with conductive yarns as transmission channels. The design and implementation of the physical and MAC layers is described. The resulting circuit sends and receives data simultaneously, and experimental results indicate that the proposed system works with variable data rates, up to a maximum of 9+9 Mbps. All reported measurements were collected from working FPGA-based prototypes, and the performance achieved shows that the circuit is suitable for use in reliable high-speed low-power BAN applications. © 2012 IEEE.

Abstract
The paper presents a method for generating partial bitstreams on-line for use in systems with run-time reconfigurable FPGAs. Bitstream creation is performed at run-time by merging partial bitstreams from individual component modules. The process includes the capability to create connections between the modules by selection from a set of routes found during an off-line pre-processing step. Placement and interconnection of modules must follow a precise set of rules. While restricting the number of possible module arrangements, this approach allows bitstream, creation to be performed with relatively few computational resources. Using a demonstration system with a Virtex-II Pro FPGA with a PowerPC 405 CPU, the process of creating at run-time a partial bitstream for 22% of the device area takes 24 ms.

Abstract
A tool called BITLINKER, that creates partially reconfigurable modules from the bit-streams of individual components is described. It is also capable of performing restricted component placement and interconnect routing between the assembled components. The resulting modules are used in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically reconfigurable platform field-programmable gate arrays (FPGAs). The associated development design flow and a run-time support system that can be used to manage module activation and data communication are described. Evaluation results obtained with a Virtex-II Pro system are also reported.

Abstract
Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. The effective use of this approach is often hampered by the complexity added to the system development process and by limited tool support. The paper is concerned with several aspects related to the effective exploitation of run-time partial reconfiguration, with particular emphasis on the generation of partial configurations and the run-time utilisation of the reconfigurable resources. The paper presents an approach inspired by the traditional software development: partial configurations are produced by assembling components from a previously created library, thus enabling the embedded application developer to produce the configuration data required for run-time modifications with less effort than is needed with the conventional design flow. A tool that supports this approach is also described. A second set of issues is addressed by a run-time support library that provides facilities for managing the hardware reconfiguration process and the communication with the reconfigured circuits. The use of run-time partial reconfiguration requires a high level of system support. The paper describes one possible approach, presenting a demonstration system developed to support the present work and characterising its performance. In order to clarify the advantages of the approach to run-time reconfigiaration discussed in the paper, two small case studies are described, the first on the use of dedicated datapaths for subword operations and the second on two-dimensional pattern-matching for bilevel images. Timing measurements for both cases are included.