Abstract

Abstract
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources. © 2011 IEEE.

Abstract
The nesting (or placement) problem is an NP-hard combinatorial problem with important industrial applications, e.g. in apparel or footwear industry. This paper describes a hardware infrastructure to accelerate the processing of the underlying geometric information. The system consists of an FPGA-based reconfigurable platform enhanced by an ASIC for the processing of irregular polygons. The paper discusses the need for such a platform, establishes the main design guidelines and describes the architecture and modes of operation of both the reconfigurable infrastructure and the dedicated IC.

Abstract
The nesting problem consists of defining the cutting plan of a piece of raw material in smaller irregular shapes, and has applications in the apparel and footwear industries. Due to its NP-hard nature, the optimal solution can only be guaranteed by exhaustively trying all possible solutions and choosing the best one. Because this is impractical in real-life industrial problems, automatic approaches are based on optimization meta-heuristics that search for sub-optimal but good enough solutions. These optimization techniques rely on the construction and evaluation of several solutions, thus requiring heavy geometric manipulation of the irregular polygons that constitute the problem data. Efficient processing of this geometric information is thus necessary to make effective fully automatic approaches to nesting problems in industrial environments. This paper describes Fafner, an FPGA-based custom computing machine that is used to accelerate the geometric operations, that are in the core of heuristic solutions to the nesting problem. The system is used as an auxiliary processor attached to a low cost personal computer, and combines a custom programmable processor with an array of custom circuits for the processing of irregular polygons.

Abstract
Higher-order statistics extend the analysis methods of non-linear systems and non-gaussian signals based on the autocorrelation and power spectrum. The main drawback of their use in real time applications is the high complexity of their estimation due to the large number of arithmetic operations. This paper presents an experimental vector architecture for the estimation of the higher-order moments. The processor's core is a pipelined multiply-accumulate unit that receives four data vectors and computes in parallel the moment taps up to the fourth-order. The design of custom cache memory organization and address generation circuits has led to more than 11 operations per clock cycle. The architecture was modeled and simulated in Verilog and is presently being implemented in XILINX field-programmable gate arrays (FPGAs) and one custom integrated circuit for the multiply-accumulate unit.

Abstract
This work presents RVC (Reconfigurable Vector Coprocessor), a FPGA based custom computing machine for vector processing applications. This system was built to serve as an implementation platform for a custom vector processor designed for a digital signal processing application. Although its architecture has been in part dictated by the immediate needs of that dedicated processor, it also serves for other custom machines exhibiting similar requirements of vector processing. © 1998 IEEE.