2025
Authors
De Oliveira, GV; Pirassoli, V; Sousa, LM; Paulino, N;
Publication
DSD
Abstract
The relevance of heterogeneous architectures has significantly increased over the last decade due to stagnation of performance scaling. Concurrently, increased performance-energy tradeoff requirements driven by the growth of edge computing, with a large focus on Artificial Intelligence (AI) inference, further motivates efforts towards hardware customization. In this context, the open RISC-V Instruction Set Architecture (ISA) and its custom extension oriented paradigm are a relevant technology towards this specialization. However, customizing a processor is a lengthy process requiring Hardware Description Language (HDL) expertise. Furthermore, for validation and simulation purposes, implementing an Instruction Set Simulator (ISS) of the modified core may also be a necessity. This introduces the need for development of two unrelated codebases, increasing development time and effort. In this paper, we explore High-Level-Synthesis (HLS) to realize both the hardware and the respective simulator through a single codebase, which reduces design effort and simplifies specialization of a RISC-V through specification of custom instructions at high level. We present a C++ based design of a RISC-V core, and validate it as an ISS, as well as a hardware module synthesized for an AMD Zynq UltraScale+ Field Programmable Gate Array (FPGA) through HLS, which we integrated in a System-on-Chip (SoC), and functionally validated through a state-of-the-art set of unit tests. © 2025 IEEE.
2025
Authors
Salinas, G; Sequeira, G; Rodriguez, A; Bispo, J; Paulino, N;
Publication
2025 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, IPDPSW
Abstract
The rapid proliferation of Edge AI applications demands efficient, low-power computing architectures tailored to specific workloads. The RISC-V ecosystem is a promising solution, and has led to a fast growth of implementations based on custom instructions extensions, but with varying degrees of functionality and support which may hinder easy adoption. In this paper, we extensively review existing RISC-V extensions targeting primarily the AI domain and respective compilation flows, highlighting challenges in deployment, usability, and compatibility. We further implement and provide usable containerized environments for two of these works. To address the identified challenges, we then propose an approach for lightweight early validation of custom instructions via source-to-source transformations, without need of compiler modifications. We target our own Single Instruction Multiple Data (SIMD) accelerator, which we integrate into a CORE-V cv32e40px baseline core through custom instructions, and versus which we achieve up to 11.9x speedup for matrix-vector operations.
2025
Authors
Gallego, J; Ferreira, JP; Alves, L; Vázquez, D; Bispo, J; Rodríguez, A; Paulino, N; Otero, A;
Publication
DCIS
Abstract
Executing Artificial Intelligence (AI) at the edge is challenging due to tight energy and computational constraints. Heterogeneous platforms, particularly those incorporating Coarse-Grained Reconfigurable Arrays (CGRAs), offer a compelling trade-off between hardware specialization and programmability, supporting spatially distributed and energyefficient computation. Despite their potential, the deployment of applications on CGRA accelerators remains limited by the lack of practical toolchains and methodologies. In this work, we propose a compilation flow based on MLIR to enable the seamless integration of both C/C++ kernels and ONNX-based AI models into a RISC-V system augmented with a CGRA accelerator. Our approach extracts the underlying Data Flow Graph (DFG) from the high-level representation. It maps it onto the CGRA using an Integer Linear Programming (ILP) mapper that accounts for the accelerator's architectural constraints. A custom backend completes the toolchain by generating the necessary binaries for coordinated execution across the RISC-V processor and the CGRA. This framework enables the practical deployment of heterogeneous edge workloads, combining the flexibility of software execution with the efficiency of hardware acceleration. © 2025 IEEE.
2025
Authors
Pereira, S; Bernardes, G; Martins, JO;
Publication
Music Theory Spectrum
Abstract
2025
Authors
Carvalho, N; Sousa, J; Bernardes, G; Portovedo, H;
Publication
PROCEEDINGS OF THE 20TH INTERNATIONAL AUDIO MOSTLY CONFERENCE, AM 2025
Abstract
This paper introduces Motiv, a dataset of expert saxophonist recordings illustrating parallel, similar, oblique, and contrary motions. These motions are variations of three phrases from Jesus VillaRojo's Lamento, with controlled similarities. The dataset includes 116 audio samples recorded by four tenor saxophonists, each annotated with descriptions of motions, musical scores, and latent space vectors generated using the VocalSet RAVE model. Motiv enables the analysis of motion types and their geometric relationships in latent spaces. Our preliminary dataset analysis shows that parallel motions align closely with original phrases, while contrary motions exhibit the largest deviations, and oblique motions show mixed patterns. The dataset also highlights the impact of individual performer nuances. Motiv supports a variety of music information retrieval (MIR) tasks, including gesture-based recognition, performance analysis, and motion-driven retrieval. It also provides insights into the relationship between human motion and music, contributing to real-time music interaction and automated performance systems.
2025
Authors
Ebrahimzadeh, Maral; Bernardes, Gilberto; Stober, Sebastian;
Publication
Abstract
State-of-the-art symbolic music generation models have recently achieved remarkable output quality, yet explicit control over compositional features, such as tonal tension, remains challenging. We propose a novel approach that integrates a computational tonal tension model, based on tonal interval vector analysis, into a Transformer framework. Our method employs a two-level beam search strategy during inference. At the token level, generated candidates are re-ranked using model probability and diversity metrics to maintain overall quality. At the bar level, a tension-based re-ranking is applied to ensure that the generated music aligns with a desired tension curve. Objective evaluations indicate that our approach effectively modulates tonal tension, and subjective listening tests confirm that the system produces outputs that align with the target tension. These results demonstrate that explicit tension conditioning through a dual-level beam search provides a powerful and intuitive tool to guide AI-generated music. Furthermore, our experiments demonstrate that our method can generate multiple distinct musical interpretations under the same tension condition.
The access to the final selection minute is only available to applicants.
Please check the confirmation e-mail of your application to obtain the access code.