Abstract
This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. The experiments reveal superior results in terms of speed and convergence to achieve a solution.

Abstract
In this work we study a heat diffusion system on a fractional calculus perspective. Several fractional PID tuning methodologies are investigated and compared. The simulations demonstrate the good performance of the proposed fractional algorithm.

Abstract
This paper presents an automated synthesis procedure to design radio-frequency and microwave binary-weighted single-ended switched capacitor arrays (RFSSCAs) from user top-level specifications to components sizes. The method relies on closed-form symbolic mathematical expressions of the input impedance and quality factor of the RFSSCA. The genetic synthesis tool optimizes a fitness function based on user-specified performance constraints. The method determines several optimal solutions, which are completely independent of the starting point. Moreover, infeasible specifications are unambiguously detected. To validate the proposed design algorithm, two RFSSCAs are synthesized in a 0.35 mu m CMOS technology and verified by the SpectreRF simulator of the Cadence design environment. The results show that the synthesis and simulation outcomes are in very good agreement.

Abstract
An automated synthesis procedure, based on genetic algorithms, to design optimum performance Si-integrated radio-frequency and microwave binary-weighted single-ended switched capacitor arrays (RFSSCAs), is presented in this paper. The method determines the RFSSCA circuit size and the circuit components values from the top-level system specifications. The genetic synthesis tool optimizes a fitness function based on user-specified performance constraints. Besides that, the algorithm uses a sharing scheme in order to achieve a set of optimal solutions. The solutions set, obtained by the genetic algorithm, give to the designer the liberty of choosing several possible implementations maintaining the performance objective. To confirm the circuit solutions obtained by the algorithm, two RFSSCAs are synthesized in a 2-poly 4-metal 0.35 mu m standard CMOS technology. The circuit is then simulated in SpectreRF. Since the synthesized results are in very good agreement with the simulated outcomes, it can be stated that the proposed genetic synthesis method is a very useful tool to design optimum performance KFSSCAs.

Abstract
A 13.5-15.5 GHz low phase noise digitally controlled LC VCO, designed in a 015 mu m BiCMOS technology, is presented in this paper. The resonant circuit of the VCO uses a high performance radio-frequency differential binary-weighted switched capacitor array (RFDSCA) to cover the 2 GHz tuning band with a continuous tuning voltage of 5 V. The RFDSCA circuit was optimized using a new automated synthesis method in order to guarantee a VCO with minimum phase noise. The VCO presents a typical phase noise of -116 dB/Hz @ 1MHz and a maximum tuning sensitivity of 165 MHz/V. The VCO core works with a voltage supply of 3 V and has a current consumption of 5 mA. The results demonstrate the feasibility of implementing and using high performance RFDSCAs as digital tuning elements at operating frequencies up to tens of gigahertz.

Abstract
The IEC 61131-3 standard defines a common framework for programming PLCs (Programmable Logic Controllers), which includes the complete definition of four programming languages and a state machine definition language. Industrial PLC vendors are slowly offering support for this standard, however small inconsistencies remain between their implementations, transferring programs between vendors is almost impossible due to different rile formats, and licenses are generally too expensive to allow students do install these commercial solutions on their own computers. To this end, the authors have developed an Integrated Development Environment (IDE) for the IEC 61131-3 framework, which is being offered to the general public under the GNU Public License (GPL). The IDE consists of a Graphical User Interface (GUI) and a backend compiler. Using the GUI the user may develop programs in any of the four programming languages, as well as the state machine definition language. The backend compiler is used to convert these programs into equivalent C++ programs which may later be compiled and executed on various platforms.