Abstract
In this paper, a printed two C-shaped monopoles array for WLAN MIMO application has been proposed. By using the neutralization technique, high isolation between the two antenna elements has been achieved while the distance between them is only 0.09(lambda 2.4GHz). The experiment results indicate that the proposed antenna array has -10dB bandwidth from 2.34 to 2.55 GHz and has an isolation less than -12 dB over the entire required operation band. The proposed antenna has a compact size of 30x14 mm(2) and can be easily integrated into wireless devices.

Abstract
In an optical transceiver, the power consumption related to the operation of the laser device takes a significant parcel of the total consumed power. Thus, in optical networks where a large number of transceiver devices are interconnected, e.g. large distributed sensor networks, it is of great importance to reduce this power consumption. In this work an analysis and simulation results are presented regarding the operation of a bias-free vertical-cavity surface-emitting laser (VCSEL) device, which is based on a previously developed model. The impact on bit-error rate (BER) of the increased turn-on jitter due to the bit-pattern and spontaneous emission is considered. A method for mitigating the eye-diagram distortion penalty based on the received signal equalization is also illustrated.

Abstract
A reconfigurable dual-band monopole array with high isolation for WLAN MIMO application is proposed. This antenna array contains two C-shaped monopoles with a shorting line, on which two RF switches were integrated, connecting the two antenna elements that are separated by a distance of 0.09 lambda(2.4GHz). High isolation at 2.4 or 5.2 GHz bands can be achieved by changing the states of the RF switches. Experiment results indicate that the proposed antenna array has a - 10 dB bandwidth that covers the required frequencies for dual-band WLAN applications with an isolation higher than 20 dB over the lower operation bands when the RF switches are 'ON', and an isolation higher than 17 dB at the higher operation band when the switches are 'OFF'.

Abstract
This article presents a platform designed for context-aware and digital rights management-enabled content adaptation based on MPEG-21's Digital Item Adaptation scheme and a unique profiling approach.

Abstract
In order to obtain depth information about a scene in computer vision, one needs to process pairs of stereo images. The calculation of dense depth maps in real-time is computationally challenging as it requires searching for matches between objects in both images. The task is significantly simplified if the images are rectified, a process which horizontally aligns the objects in both images. The process of stereo images rectification has several steps with different computational requirements. The steps include 2D searches for high fidelity matches, precise matrix calculations, and fast pixel coordinate transformations and interpolations. In this project, the complete process is effectively implemented in a Spartan-3 FPGA, taking advantage of a MicroBlaze soft core for slow but precise calculations, and of fast dedicated hardware support for achieving the real-time requirements. The implemented system successfully performs real-time rectification on the images from two video cameras, with a resolution of 640×480 pixels and a frame rate of 25 fps, and is easily configured for videos with higher resolutions. The experimental results show very good quality, with rectified images having a maximum vertical disparity of two pixels, thereby showing that stereo image rectification can be efficiently achieved in an low-resource FPGA (with 64KB for program instructions and data). © 2010 IEEE.

Abstract
This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution is a custom-built hardware architecture for the disparity map calculation, and an optional post-processing stage that coarsens the output to improve resilience against spurious results. The system was described in Verilog, and a prototype implemented on a Xilinx Virtex-II Pro FPGA proved capable of processing 640x480 black-and-white images at a maximum frame rate of 40 fps, using 3x3 matching windows and detecting disparities of up to 135 pixels. ©2010 IEEE.