2006
Authors
Fonseca, B; Carrapatoso, E;
Publication
Groupware: Design, Implementation, and Use
Abstract
To improve their efficiency and competitiveness, organizations are increasingly interested in applications that support team work, usually know as groupware. Beside interoperability, familiarity with the application and users' mobility support, a feature that is of outmost importance in groupware is the notification of events produced by cooperative activities. Web Services have emerged recently to support the exchange of data in distributed environments using common Internet technologies and have been used mainly to build business-to-business applications. However, Web Services have capabilities that make them suitable to meet the requirements posed by groupware applications, a field where little work has been carried out. This article describes a model for developing cooperative applications based on Web Services technology and using asynchronous notification of events, and presents a brief description of the implementation of the support services for that model and of a prototype application that uses them.
2006
Authors
Fonseca, B; Carrapatoso, E;
Publication
SMPTE MOTION IMAGING JOURNAL
Abstract
Desktop video editing plays an important role in the digital video market, and cooperative applications are important for organizations. Cooperative video editing tools can be an interesting solution for large broadcasters or for remote reporting, and such commercial products are lacking. This paper describes a cooperative video editing tool, Coview, which uses Web services to provide the cooperative functionalities. For this purpose, an overview is given of the basic issues of Web Services and Computer Supported Cooperative Work. Then, the Web Services-based cooperative infrastructure and the Coview prototype is described. Finally, some experimental results and concluding remarks are presented.
2006
Authors
Cardoso, JMP; Constantinides, GA;
Publication
INTERNATIONAL JOURNAL OF ELECTRONICS
Abstract
2006
Authors
Bertels, K; Cardoso, JMP; Vassiliadis, S;
Publication
Lecture Notes in Computer Science
Abstract
2006
Authors
da Silva, MV; Ferreira, RS; Garcia, A; Cardoso, JMP;
Publication
2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006
Abstract
Coarse-grained reconfigurable array architectures are currently focus of intensive research. They have already proven performance improvements and energy savings over traditional architectures. However, coarse-grained arrays vary widely in the number and characteristics of the processing elements and routing topologies used. This work presents a flexible mapping environment for design space exploration of coarse-grained, data-driven, reconfigurable array architectures. The mapping included in the environment presented in this paper takes advantage of Java and XML technologies to enable an efficient architectural trade-off analysis. This approach does not focus on neither a specific mapping algorithm nor a specific architecture, but on an open environment where users can add their own mapping algorithms and architecture patterns. A genetic algorithm for placement is presented. A number of DSP benchmarks are used to explore a range of mesh architectures and to validate the approach. The experiments show a fast, scalable and flexible mapping environment to explore new mesh array patterns, homogeneous and heterogeneous architectures. © 2006 IEEE.
2006
Authors
Lopes, JJ; Silva, JLE; Marques, E; Cardoso, JMP;
Publication
6TH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS
Abstract
High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. Powerful high-level language to RTL generators are now emerging. One of the promises of these tools is to allow software and systems engineers to implement algorithms quickly in a familiar language and target the design to a programmable device. The generators available today support syntaxes with different degrees of fidelity to the original language. This paper focuses on the efficient use of C to RTL generators that have a high degree of fidelity to the original C language. The objective of this project is to study some tools that starting from languages of high level as ANSI-C, and generate FPGA accelerating software applications automatically. In this paper are presented tools and partial results of the hardware generated by them.
The access to the final selection minute is only available to applicants.
Please check the confirmation e-mail of your application to obtain the access code.