Abstract
It is generally considered that a key component of electronic government in the future will be electronic voting, as a means of facilitating the participation of citizens in elections and public debates. However, a long path has to be pursued before electronic voting, particularly if based on Internet, is accepted as a reliable system alternative to conventional methods. In this paper, we propose a new and simple platform, based on open software, which can be used primarily in small to medium sized communities, as a means to build confidence and experience for future larger elections. We try to provide adequate answers to multiple requirements, such as accuracy, democracy, privacy, verifiability and mobility. This can be done by establishing a distributed system which supports the different roles of a voting system and by using cryptography techniques in the interactions between these components.

Abstract
This paper presents recent advances in a compiler infrastructure to map algorithms described in a Java subset to FPGA-based platforms. We explain how delays and resources are estimated to guide the compiler through scheduling and temporal partitioning. The compiler supports complex analytical models to estimate resources and delays for each functional unit. The paper presents experimental results for a number of benchmarks. Those results also arrise a question when performing temporal partitioning: shall we try to group as many computational structures in the same configuration or shall we have several configurations?

Abstract
This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

Abstract
It is predicted that by the year 2010, 90% of the overall program code developed will be for embedded computing systems. This fact requires urgent changes in the organization of the current computer science curriculums, as advocated by a number of academics. The changes will help students deal with the idiosyncrasies of embedded systems, which requires knowledge about the computation engine, its energy consumption model, performance, interfaced artifacts, reconfigurable hardware programming, etc. This paper discusses some important issues to be included in modern computer science programs, in order to prepare students to be able to program future embedded computers. In particular, we present an approach we are attempting to implement at our institution. We also illustrate infrastructures that permit students to implement complex examples and gain deep knowledge about the topics being taught. Finally, with this paper we hope to foment a fruitful discussion on those issues. Copyright 2005 ACM.

Abstract

Abstract
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over microprocessors and shorter programming cycles than FPGA-based platforms. As with other architectures, in data-driven architectures loop pipelining plays an important role to improve performance. Usually this kind of pipelining can be achieved using the dataflow software pipelining technique or other software pipelining approaches. Although performance improvements are achieved, those techniques heavily depend on the insertion of pipelining stages and thus require complex balancing efforts. Furthermore, those techniques statically define the pipelining and do not take fully advantage of the dynamic scheduling attainable by the data-driven concept. This paper presents a novel scheme to pipeline loops in data-driven architectures, orchestrated by a handshaking protocol. Using the new approach, self loop pipelining is naturally achieved. The scheme is based on duplicating cyclic hardware structures, in order they are autonomously executed, with synchronization being achieved by the data flow. It can be applied to nested loops, requires less aggressive pipeline balancing efforts than usual software pipelining techniques, and innermost loops with conditional structures can be pipelined without conservative pipelining implementations. We show results of using the proposed technique when mapping algorithms in imperative programming languages to the PACT eXtreme Processing Platform (XPP). The results confirm improvements over the use of conventional loop pipelining techniques. Better performance and fewer resources are achieved in a number of cases. Copyright 2005 ACM.