Abstract
Coarse-grained reconfigurable array architectures are currently focus of intensive research. They have already proven performance improvements and energy savings over traditional architectures. However, coarse-grained arrays vary widely in the number and characteristics of the processing elements and routing topologies used. This work presents a flexible mapping environment for design space exploration of coarse-grained, data-driven, reconfigurable array architectures. The mapping included in the environment presented in this paper takes advantage of Java and XML technologies to enable an efficient architectural trade-off analysis. This approach does not focus on neither a specific mapping algorithm nor a specific architecture, but on an open environment where users can add their own mapping algorithms and architecture patterns. A genetic algorithm for placement is presented. A number of DSP benchmarks are used to explore a range of mesh architectures and to validate the approach. The experiments show a fast, scalable and flexible mapping environment to explore new mesh array patterns, homogeneous and heterogeneous architectures. © 2006 IEEE.

Abstract
High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. Powerful high-level language to RTL generators are now emerging. One of the promises of these tools is to allow software and systems engineers to implement algorithms quickly in a familiar language and target the design to a programmable device. The generators available today support syntaxes with different degrees of fidelity to the original language. This paper focuses on the efficient use of C to RTL generators that have a high degree of fidelity to the original C language. The objective of this project is to study some tools that starting from languages of high level as ANSI-C, and generate FPGA accelerating software applications automatically. In this paper are presented tools and partial results of the hardware generated by them.

Abstract
This paper presents a methodology to implement PID (Proportional, Integral, Derivative) controllers in FPGAs (Field-Programmable Gate Arrays) using fixed-point numerical representation. The Matlab/Simulink environment is used for modeling, simulation and evaluation the performance provided by different fixed-point representations using a given control process. A static bit-width analyzer is used to give a specialized fixed-point representation for each operand/operator in the controller system. After bit-width analysis, a VHDL representation of the system is generated. Results show that the proposed methodology leads to shorten design cycles achieving important resource savings by employing specialized fixed-point representations.

Abstract
Recent intrusion detection systems (IDS) use regular expressions instead of static patterns as a more efficient way to represent hazardous packet payload contents. This paper focuses on regular expressions pattern matching engines implemented in reconfigurable hardware. We present a Nondeterministic Finite Automata (NFA) based implementation, which takes advantage of new basic building blocks to support more complex regular expressions than the previous approaches. Our methodology is supported by a tool that automatically generates the circuitry for the given regular expressions, outputting VHDL representations ready for logic synthesis. Furthermore, we include techniques to reduce the area cost of our designs and maximize performance when targeting FPGAs. Experimental results show that our tool is able to generate a regular expression engine to match more than 500 IDS regular expressions (from the Snort ruleset) using only 25K logic cells and achieving 2 Gbps throughput on a Virtex2 and 2.9 on a Virtex4 device. Concerning the throughput per area required per matching non-Meta character, our design is 3.4 and 10x more efficient than previous ASIC and FPGA approaches, respectively.

Abstract

Abstract