Abstract

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Abstract

Abstract

Abstract
Three articles focusing on interesting architectural features and/or execution techniques which configurable architectures make more accessible are discussed. The Applied Reconfigurable Computing (ARC) workshop series has been devoted to addressing the role of software programmers and hardware designers in implementing configurable and reconfigurable architectures while still recognizing the value of configurable computing basic techniques and application areas. The first article, by Wu, Kanstein, Madsen and Berekovic, describes the application of multithreading to a coarse-grain reconfigurable architecture. The second article by Chikhi, Derrien, Noumsi and Quinton, is devoted to a specific architectural feature, the inclusion of FLASH memory to facilitate the implementation of image-based algorithms, an application that matches very well with FPGA configurable technology. Finally, a third article in this track by Hur, Wong and Vassiliadis, explores the use of point-to-point interconnects in a contemporary FPGA.

Abstract
Regular expressions are being used in many applications to specify multiple and complex text patterns in a compact way. In some of these applications large sets of regular expressions need to be evaluated to detect matched content. Specialised hardware engines are employed when software-based regular expression engines are not able to meet the performance requirements imposed by such applications. Since the sets of regular expressions are periodically modified and/or extended, FPGAs are an attractive hardware solution to achieve both programmability and high-performance demands. However, efficient automatic synthesis tools are of paramount importance to achieve fast prototyping of regular expression engines on these devices. This paper presents an overview of the synthesis of regular expressions with the aim of achieving high-performance engines for FPGAs. We focus on describing current solutions, proposing new solutions for constraint repetitions and overlapped matching, and discussing a number of challenges and open issues. As a case study, we present FPGA implementations of the regular expressions included in two rule-sets of network intrusion detection system (NIDS), Bleeding Edge and Snort, obtained using a state-of-the-art synthesis approach.