Abstract
In the decades to come spatial limitation poses a major challenge for islands, especially where tourism dominates and many heritage and natural conservation sites exist. Simultaneously, alternatives to lower energy import dependency are sought. Since onshore technologies are confronted by spatial limitation, the focus might shift towards integrating offshore technologies. Although most of those technologies lack market maturity, the benefit to be installed (far) off the coast is immense. Yet, it is a challenge to select the most appropriate technology for any given site location. Thereby, it is not pre-dominantly a matter of economic and environmental concerns, rather than an assessment of site conditions and resource characteristics. A set of indicators for, both, conditions and characteristics has been established that allows pre-selecting and comparing the suitability of various offshore technologies. Hence, energy planners will be able to select from the most appropriate technologies when planning for a sustainable future. © 2015 Taylor & Francis Group, London.

Abstract
There is growing evidence that internationalization of small and medium enterprises (SMEs) has become a priority to gain competitive advantage. However, SMEs still face major challenges and obstacles during these processes. This paper proposes a model of collaborative networks for internationalization processes of SMEs, mediated by industrial enterprise associations (IEAs), in order to improve decision-making processes. First, a systematic literature review (SLR) was performed to study the impact that networks and collaboration have in the decision-making process of internationalization. Then, the model was developed using adequate information and knowledge management tools. Finally, to understand the relevance of the proposed model, data were gathered through interviews to key persons in companies of the IT/electronics and textile industries. Results showed that collaborative networks can represent an important facilitator in the internationalization of SMEs and that IEAs can have a fundamental role for promoting collaboration in this domain, between associated SMEs.

Abstract

Abstract
This paper describes the development of a mobile indoor navigation system, supported by a GIS and built using only open source tools. For the sake of simplicity a single building was chosen for the tests converting the floors to digital information from paper plans. The rooms geometry was saved on a proper database with all the adjacent information associated, which can in turn be provided to the clients application by APIs and Web Services. The system is able to calculate the most adequate path between any of the rooms taking into account the user profile which is defined by it's degree of mobility (eg. wheelchair). By reading a QR code placed in key places inside the building the user can obtain, on a mobile phone, his current position and receive orientations to any room that he might want to go. The directions hints are complemented with the presentation of real pictures associated to key locations in the path to validate that the correct path is taken by the user. (C) 2015 The Authors. Published by Elsevier B.V.

Abstract
The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code and still ensures program portability over different target reconfigurable fabrics. However, the problem is very challenging, as suitable sequences of GPP instructions need to be translated/mapped to hardware, possibly at runtime. Thus, all mapping steps, from compiler analysis and optimizations to hardware generation, need to be both efficient and fast. This paper introduces some of the most representative approaches for binary acceleration using reconfigurable hardware, and presents our binary acceleration approach and the latest results. Our approach extends a GPP with a Reconfigurable Processing Unit (RPU), both sharing the data memory. Repeating sequences of GPP instructions are migrated to an RPU composed of functional units and interconnect resources, and able to exploit instruction-level parallelism, e.g., via loop pipelining. Although we envision a fully dynamic system, currently the RPU resources are selected and organized offline using execution trace information. We present implementation prototypes of the system on a Spartan-6 FPGA with a MicroBlaze as GPP and the very encouraging results achieved with a number of benchmarks.

Abstract
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