Cookies
O website necessita de alguns cookies e outros recursos semelhantes para funcionar. Caso o permita, o INESC TEC irá utilizar cookies para recolher dados sobre as suas visitas, contribuindo, assim, para estatísticas agregadas que permitem melhorar o nosso serviço. Ver mais
Aceitar Rejeitar
  • Menu
Publicações

Publicações por Nuno Miguel Paulino

2016

Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration

Autores
Cardanha Paulino, NM;

Publicação

Abstract

2011

From Instruction Traces to Specialized Reconfigurable Arrays

Autores
Bispo, J; Cardanha Paulino, NM; Cardoso, JMP; Ferreira, JC;

Publicação
2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011

Abstract
This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9x and 18.2x for a Micro Blaze CPU without cache. We estimate speedups from 1.03x to 2.01x, when comparing to the best estimated performance achieved with a single Micro Blaze. © 2011 IEEE.

2022

BacalhauNet: A tiny CNN for lightning-fast modulation classification

Autores
Jose Rosa; Daniel Granhao; Guilherme Carvalho; Tiago Gon?alves; Monica Figueiredo; Luis Conde Bento; Nuno Paulino; Luis M. Pessoa;

Publicação
ITU Journal on Future and Evolving Technologies

Abstract
Deep learning methods have been shown to be competitive solutions for modulation classification tasks, but suffer from being computationally expensive, limiting their use on embedded devices. We propose a new deep neural network architecture which employs known structures, depth-wise separable convolution and residual connections, as well as a compression methodology, which combined lead to a tiny and fast algorithm for modulation classification. Our compressed model won the first place in ITU's AI/ML in 5G Challenge 2021, achieving 61.73? compression over the challenge baseline and being over 2.6? better than the second best submission. The source code of this work is publicly available at github.com/ITU-AI- ML-in-5G-Challenge/ITU-ML5G-PS-007-BacalhauNet.

2022

A Batch of Integer Data Sets for Clustering Algorithms

Autores
Paulino, N;

Publicação

Abstract

2022

A Dataset of Phase Samples using an 8-Element Uniform Circular Antenna Array and a Bluetooth Low Energy 5.1 Nordic nRF52811 Based Receiver

Autores
Paulino, N;

Publicação

Abstract

2023

Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper)

Autores
Bispo, J; Paulino, N; Sousa, LM;

Publicação
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2023, January 17, 2023, Toulouse, France.

Abstract
The C/C++ compilation stack (Intermediate Representations (IRs), compilation passes and backends) is encumbered by a steep learning curve, which we believe can be lowered by complementing it with approaches such as source-to-source compilation. Source-to-source compilation is a technology that is widely used and quite mature in certain programming environments, such as JavaScript, but that faces a low adoption rate in others. In the particular case of C and C++ some of the identified factors include the high complexity of the languages, increased difficulty in building and maintaining C/C++ parsers, or limitations on using source code as an intermediate representation. Additionally, new technologies such as Multi-Level Intermediate Representation (MLIR) have appeared as potential competitors to source-to-source compilers at this level. In this paper, we present what we have identified as current challenges of source-to-source compilation of C and C++, as well as what we consider to be opportunities and possible directions forward. We also present several examples, implemented on top of the Clava source-to-source compiler, that use some of these ideas and techniques to raise the abstraction level of compiler research on complex compiled languages such as C or C++. The examples include automatic parallelization of for loops, high-level synthesis optimisation, hardware/software partitioning with run-time decisions, and automatic insertion of inline assembly for fast prototyping of custom instructions. © João Bispo, Nuno Paulino, and Luís Miguel Sousa.

  • 6
  • 7