Abstract
In this paper, we report the impact of the parasitic capacitances in the modeling and analysis of advanced floating gate (FG) non-volatile memory (NVM) devices, especially on the coupling ratio. Due to the poor accuracy of the existing capacitance model when compared to practice, an approach to include the parasitic capacitances has been established. Measurement results from two transistor (2T) Fowler-Nordheim (FN) tunneling operated flash memory show a good improvement in the model accuracy. The parasitic capacitances depend very much on the floating gate dimension, and the spacing to the neighboring elements in the flash cell array. The growing influence of the parasitic capacitances and the subsequent degradation of the existing model accuracy can be expected for the cells dimensions in future process technologies. With the accurate calculation method for the parasitic capacitances proposed in this paper, the cell characteristics can be more accurately modeled, andthe degradation of the cell can be accurately studied. ©2009 IEEE.

Abstract
The use of textile yarns as data transmission media enables the design of non-obtrusive well-fitting garments as wearable systems. However, textile conductive yarns show impedances higher than those presented by common metal conductors and these values can change with the textile condition and level of stretching, affecting the integrity of the transmitted signal. This work proposes a built-in self-test methodology to test textile yarn interconnections for conventional stuck-at, open and short faults, as well as to verify signal integrity. The test procedure being proposed relies on sampling to generate a digital signal that results from comparing the received signal with pre-defined voltage levels. The obtained signature allows to verify signal integrity parameters: VLmax, VHmin and rise and fall times. Simulation results confirm the validity of the methodology being proposed. © 2012 IEEE.

Abstract
A new inductive coupling based wireless system is being developed to monitor the condition status of aortic stent-grafts. It relies on the measure of the stent-graft's outer pressure using a capacitive sensor placed in a LC resonant circuit. The work presented herein addresses the testing of the LC sensor circuit to diagnose whether observed pressure deviations are due to defects occurring in the sensor's inductor and capacitor or to an actual degradation of the stent-graft. © 2012 IEEE.

Abstract
Peak voltage sensors, namely diode based detectors, have been used for in-circuit testing of RF circuits. These detectors are simple to implement but provide a limited accuracy. On the other hand, the power inferred from these measurements assumes that impedance is known. This work presents a comparison between measurements obtained with peak voltage and true power detectors. The trade-off between observing one and the other are discussed, namely as far as information concerning the output load is concerned. Simulation results, acquired with the model of a prototype demonstration chip, show that more accurate information is obtained with power rather than voltage measurements in case load impedance variations occur. Experimental results obtained with a prototype chip are currently being obtained. ©2010 IEEE.

Abstract
The present paper describes developments carried-out on estimating 1 dB compression and third-order intercept points after the cross-correlation between power supply dynamic current and output voltage of radio-frequency power amplifier. The underlining theory and a circuit that allows implementing this measurement on-chip are presented. Simulation results, including the analysis of optimum stimuli amplitudes and the Monte Carlo analysis to circuits' process variations are presented. These show that good accuracy can be obtained with relatively simple measurement conditions.

Abstract
The estimation of 1 dB compression and third-order intercept points can be obtained after the cross-correlation between dynamic current and output voltage of radio frequency power amplifiers. Estimation is performed using power measures and not power inferred from voltage measures. The underlining theory and a correlator that allows implementing this measurement on-chip are presented. The trade-off between measuring voltage or the actual power is also discussed. It is also shown that different information concerning the output load is obtained when observing the PA's output voltage and power. Simulation results, obtained with the model of a prototype demonstration chip show that good accuracy can be obtained with relatively simple measurement conditions. These results include the analysis of optimum stimuli amplitudes and the effect of noise in estimation accuracy. © 2010 IEEE.