Abstract
This paper presents experiments carried out with a prototype test chip provided by the IEEE P1149.4 Mixed-Signal Testing Working Group, which explore the architecture of the proposed analogue boundary module to implement simultaneous observation of power supply current and output voltage, towards mixed current/voltage testing of analogue and mixed-signal circuits.

Abstract
Reducing the area overhead required by BIST structures can be achieved by reconfiguring existing hardware to perform test related control and processing functions. This work shows how the resources required for these operations can be implemented in-circuit, taking advantage of programmable logic available in the system. Structural and functional tests are performed using correlation to obtain iDD and uOUT cross-correlation signatures, and to measure gain, phase, and total harmonic distortion. © 2000 IEEE.

Abstract
Analog-to-digital converter (ADC) characterization is usually performed using stationary stimuli like sine waves. However, the use of a non-stationary stimulus, besides providing testing conditions closer to those found in real applications, can lead to interesting improvements in ADC testing speed, This kind of signal needs proper processing techniques in order to extract useful information. In this paper we propose the use of joint time-frequency analysis (JTFA) for this purpose. The basic principles of the technique, and how it can be used in ADC testing are presented. in particular, a method for characterising an ADC on its entire bandwidth using a single stimulus is described.

Abstract
A method for the in-circuit functional testing of SigmaDelta modulators is described which can be built in large integrated circuits or systems-on-chip. It allows for measuring gain and phase, as well as total harmonic distortion and signal to noise and harmonic distortion ratio parameters. This method can be built in-circuit using existing computational resources, such as digital signal processors or (re)configurable logic, which can therefore be used to implement both mission and test operations. Both simulation and experimental results were obtained which are in close agreement with those expected from the theory.

Abstract
The estimation of the harmonic content of an ADC output is fundamental to evaluate its suitability to perform according the requirements specified for an application. The use of the traditional frequency analysis leads to a large hardware overhead due to the amount of on-chip processing being involved, or to a large quantity of data to be transferred in case the processing is performed in a tester. This paper presents an algorithm capable of estimating the harmonics with similar accuracy but with the advantage of being more suitable for a BIST implementation, since it requires a reduced number of on-chip operations, and that only a small set of values has to be supplied outside the chip for further processing. It relies, on the fact that harmonics generated by an ADC are mathematical related with the polynomial coefficients of its transfer function. ADC offset and gain errors can also be measured.

Abstract
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an AID converter is described as an example.