Abstract
A new wearable data capture system for gait analysis is being developed. It consists of a pantyhose with embedded conductive yarns interconnecting customized sensing electronic devices that capture inertial and electromyographic signals and sends aggregated information to a personal computer through a wireless link. The use of conductive yarns to build the myoelectric electrodes and the interconnections of the wired sensors network, as well as the topology and functionality of the sensor modules are presented.

Abstract
This paper presents a network circuit for wearable low-power BAN (Body Area Networks) applications, geared towards mesh network topologies with conductive yarns as transmission channels. The design and implementation of the physical and MAC layers is described. The resulting circuit sends and receives data simultaneously, and experimental results indicate that the proposed system works with variable data rates, up to a maximum of 9+9 Mbps. All reported measurements were collected from working FPGA-based prototypes, and the performance achieved shows that the circuit is suitable for use in reliable high-speed low-power BAN applications. © 2012 IEEE.

Abstract
This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.

Abstract
Instructions for concurrent processing of smaller data units than whole CPU words are useful in areas like multimedia processing and cryptography. Since the processors used in FPGA-based embedded systems lack support for such applications, this paper proposes mapping sequences of subword operations to a set of hardware components and generating the corresponding FPGA partial configurations at run-time. The technique is aimed at adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. New partial configurations for circuits implementing sets of subword operations are created by merging together the relocated partial configurations of the hardware components (from a predefined library), and the configurations of the switch matrices used for the connections between the components. The paper presents and discusses results obtained for a 300 MHz PowerPC CPU in a Virtex-II Pro platform FPGA. For the set of benchmarks analyzed, the complete configuration creation process takes between 1 s and 24 s. The run-time generated hardware versions achieve speed-ups between 11 and 73 over the software versions.

Abstract
Cellular Genetic Algorithms (cGAs) exhibit a natural parallelism that makes them interesting candidates for hardware implementation, as several processing elements can operate simultaneously on subpopulations shared among them. This paper presents a scalable architecture for a cGA, suitable for FPGA implementation. A regular array of custom designed processing elements (PEs) works on a population of solutions that is spread into dual-port memory blocks locally shared by adjacent PEs. A travelling salesman problem with 150 cities was used to verify the implementation of the proposed cGA on a Virtex-6 FPGA, using a population of 128 solutions with different levels of parallelism (1, 4, 16 and 64 PEs). Results have shown that an increase of the number of PEs does not degrade the quality of the convergence of the iterative process, and that the throughput increases almost linearly with the number of PEs. Comparing with a software implementation running in a PC, the cGA with 64 PEs has shown a 45x speedup.

Abstract
The main problem behind Automatic Transcription (Multiple Fundamental Frequency - F0 - Estimation) relies on its complexity. Harmonic collision and partial overlapping create a frequency lattice that is almost impossible to de-construct. Although traditional approaches to this problem of rely mainly in Digital Signal Processing (DSP) techniques, evolutionary algorithms have been applied recently to this problem and achieved competitive results. We describe all evolutionary approaches to the problem of automatic music transcription and how some were improved so they could achieve competitive results. Finally, we show how the best evolutionary approach performs on piano transcription, when compared with the state-of-the-art.