Abstract
Leveraging the capabilities of Knowledge Distillation (KD) strategies, we devise a strategy to fight the recent retraction of face recognition datasets. Given a pretrained Teacher model trained on a real dataset, we show that carefully utilising synthetic datasets, or a mix between real and synthetic datasets to distil knowledge from this teacher to smaller students can yield surprising results. In this sense, we trained 33 different models with and without KD, on different datasets, with different architectures and losses. And our findings are consistent, using KD leads to performance gains across all ethnicities and decreased bias. In addition, it helps to mitigate the performance gap between real and synthetic datasets. This approach addresses the limitations of synthetic data training, improving both the accuracy and fairness of face recognition models.

Abstract
This study investigates the effects of occlusions on the fairness of face recognition systems, particularly focusing on demographic biases. Using the Racial Faces in the Wild (RFW) dataset and synthetically added realistic occlusions, we evaluate their effect on the performance of face recognition models trained on the BUPT-Balanced and BUPT-GlobalFace datasets. We note increases in the dispersion of FMR, FNMR, and accuracy alongside decreases in fairness according to Equalized Odds, Demographic Parity, STD of Accuracy, and Fairness Discrepancy Rate. Additionally, we utilize a pixel attribution method to understand the importance of occlusions in model predictions, proposing a new metric, Face Occlusion Impact Ratio (FOIR), that quantifies the extent to which occlusions affect model performance across different demographic groups. Our results indicate that occlusions exacerbate existing demographic biases, with models placing higher importance on occlusions in an unequal fashion across demographics.

Abstract
The development of deep learning algorithms has extensively empowered humanity's task automatization capacity. However, the huge improvement in the performance of these models is highly correlated with their increasing level of complexity, limiting their usefulness in human-oriented applications, which are usually deployed in resource-constrained devices. This led to the development of compression techniques that drastically reduce the computational and memory costs of deep learning models without significant performance degradation. These compressed models are especially essential when implementing multi-model fusion solutions where multiple models are required to operate simultaneously. This paper aims to systematize the current literature on this topic by presenting a comprehensive survey of model compression techniques in biometrics applications, namely quantization, knowledge distillation and pruning. We conduct a critical analysis of the comparative value of these techniques, focusing on their advantages and disadvantages and presenting suggestions for future work directions that can potentially improve the current methods. Additionally, we discuss and analyze the link between model bias and model compression, highlighting the need to direct compression research toward model fairness in future works.

Abstract
This study investigates the use of SHAP (SHapley Additive exPlanations) values as an explainable artificial intelligence (xAI) technique applied on a facial attribute classification task. We analyse the consistency of SHAP value distributions across diverse classifier architectures that share the same feature extractor, revealing that key features driving attribute classification remain stable regardless of classifier architecture. Our findings highlight the challenges in interpreting SHAP values at the individual sample level, as their reliability depends on the model's ability to learn distinct class-specific features; models exploiting inter-class correlations yield less representative SHAP explanations. Furthermore, pixel-level SHAP analysis reveals that superior classification accuracy does not necessarily equate to meaningful semantic understanding; notably, despite FaceNet exhibiting lower performance than CLIP, it demonstrated a more nuanced grasp of the underlying class attributes. Finally, we address the computational scalability of SHAP, demonstrating that KernelExplainer becomes infeasible for high-dimensional pixel data, whereas DeepExplainer and GradientExplainer offer more practical alternatives with trade-offs. Our results suggest that SHAP is most effective for small to medium feature sets, providing interpretable and computationally manageable explanations.

Abstract
The relevance of heterogeneous architectures has significantly increased over the last decade due to stagnation of performance scaling. Concurrently, increased performance-energy tradeoff requirements driven by the growth of edge computing, with a large focus on Artificial Intelligence (AI) inference, further motivates efforts towards hardware customization. In this context, the open RISC-V Instruction Set Architecture (ISA) and its custom extension oriented paradigm are a relevant technology towards this specialization. However, customizing a processor is a lengthy process requiring Hardware Description Language (HDL) expertise. Furthermore, for validation and simulation purposes, implementing an Instruction Set Simulator (ISS) of the modified core may also be a necessity. This introduces the need for development of two unrelated codebases, increasing development time and effort. In this paper, we explore High-Level-Synthesis (HLS) to realize both the hardware and the respective simulator through a single codebase, which reduces design effort and simplifies specialization of a RISC-V through specification of custom instructions at high level. We present a C++ based design of a RISC-V core, and validate it as an ISS, as well as a hardware module synthesized for an AMD Zynq UltraScale+ Field Programmable Gate Array (FPGA) through HLS, which we integrated in a System-on-Chip (SoC), and functionally validated through a state-of-the-art set of unit tests. © 2025 IEEE.

Abstract
The rapid proliferation of Edge AI applications demands efficient, low-power computing architectures tailored to specific workloads. The RISC-V ecosystem is a promising solution, and has led to a fast growth of implementations based on custom instructions extensions, but with varying degrees of functionality and support which may hinder easy adoption. In this paper, we extensively review existing RISC-V extensions targeting primarily the AI domain and respective compilation flows, highlighting challenges in deployment, usability, and compatibility. We further implement and provide usable containerized environments for two of these works. To address the identified challenges, we then propose an approach for lightweight early validation of custom instructions via source-to-source transformations, without need of compiler modifications. We target our own Single Instruction Multiple Data (SIMD) accelerator, which we integrate into a CORE-V cv32e40px baseline core through custom instructions, and versus which we achieve up to 11.9x speedup for matrix-vector operations.