Abstract

Abstract
The emergence of pervasive computing, the rapid advancements in broadband and mobile networks and the incredible appeals of smart devices are driving unprecedented universal access and delivery of online-based media resources. As more and more media services continue to flood the Web, mobile users will continue to waste invaluable time, seeking content of their interest. To deliver relevant media items offering richer experiences to mobile users, media services must be equipped with contextual knowledge of the consumption environment as well as contextual preferences of the users. This article investigates context-aware recommendation techniques for implicit delivery of contextually relevant online media items. The proposed recommendation services work with a contextual user profile and a context recognition framework, using case base reasoning as a methodology to determine user's current contextual preferences, relying on a context recognition service, which identifies user's dynamic contextual situation from device's built-in sensors. To evaluate the proposed solution, we developed a case-study context-aware application that provides personalized recommendations adapted to user's current context, namely the activity he/she performs and consumption environment constraints. Experimental evaluations, via the case study application, real-world user data, and online-based movie metadata, demonstrate that context-aware recommendation techniques can provide better efficacy than the traditional approaches. Additionally, evaluations of the underlying context recognition process show that its power consumption is within an acceptable range. The recommendations provided by the case study application were assessed as effective via a user study, which demonstrates that users are pleased with the contextual media recommendations.

Abstract
This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks. A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP's data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60x and 1.18x for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.

Abstract
Solving complex optimization problems with genetic algorithms (GAs) with custom computing architectures is a way to improve the execution time of this metaheuristic, which is known to consume considerable amounts of time to converge to final solutions. In this work, we present a scalable computing array architecture to accelerate the execution of cellular GAs (cGAs), a variant of genetic algorithms which can conveniently exploit the coarse- grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and is used as an auxiliary processor of an embedded CPU (MicroBlaze). To handle different optimization problems, a high- level synthesis (HLS) design flow is proposed where the problem- dependent operations are specified in C++ and synthesised to custom hardware, thus requiring a minimum knowledge of digital design for FPGAs. The minimum energy broadcast (MEB) problem in wireless ad hoc networks is used as a case study. An existing software implementation of a GA to solve this problem is ported to the proposed computing array to demonstrate its effectiveness and the HLS- based design flow. Implementation results in a Virtex- 6 FPGA show significant speedups, while finding solutions with improved quality.

Abstract
The proliferation of new wireless communication technologies and services led to a boost in the number of different available communication standards and spectrum usage. As the electromagnetic spectrum is a finite resource, concerns about its efficient management became an important aspect. Given this scenario, Cognitive Radio emerged as a solution for future wireless communication devices, by supporting multiple standards and improving spectrum utilization through opportunistic wireless access. The purpose of this research is to study and design a reconfigurable FPGA-based NC-OFDM baseband processor meeting the requirements of next generation Cognitive Radio devices in terms of multi-carrier, multi-standard communications and spectral agility in changing environments. The processor will be the core of a flexible NC-OFDM transceiver for future 5G communications with support for spectrum aggregation and run-time selection of modulation schemes and active sub-carriers. The goal is to achieve higher levels of system adaptability, upgradeability and efficiency, by employing dynamic partial reconfiguration of FPGAs.

Abstract
The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code and still ensures program portability over different target reconfigurable fabrics. However, the problem is very challenging, as suitable sequences of GPP instructions need to be translated/mapped to hardware, possibly at runtime. Thus, all mapping steps, from compiler analysis and optimizations to hardware generation, need to be both efficient and fast. This paper introduces some of the most representative approaches for binary acceleration using reconfigurable hardware, and presents our binary acceleration approach and the latest results. Our approach extends a GPP with a Reconfigurable Processing Unit (RPU), both sharing the data memory. Repeating sequences of GPP instructions are migrated to an RPU composed of functional units and interconnect resources, and able to exploit instruction-level parallelism, e.g., via loop pipelining. Although we envision a fully dynamic system, currently the RPU resources are selected and organized offline using execution trace information. We present implementation prototypes of the system on a Spartan-6 FPGA with a MicroBlaze as GPP and the very encouraging results achieved with a number of benchmarks.