Abstract
5G heterogeneity will cover a huge diversity of use cases, ranging from enhanced-broadband to low-throughput and low-power communications. To address such requirements variety, this paper proposes a parallel-pipelined architecture for an OFDM baseband modulator with clock frequency run-time adaptation through dynamic frequency scaling (DFS). It supports a set of OFDM numerologies recently proposed for 5G communication systems. The parallel-pipelined architecture can achieve high throughputs at low clock frequencies (up to 520.3 MSamples/s at 160 MHz) and DFS allows for the adjustment of baseband processing clock frequency according to immediate throughput demands. The application of DFS increases the system’s power efficiency by allowing power savings up to 62.5%; the resource and latency overhead is negligible. © Springer International Publishing AG, part of Springer Nature 2018.

Abstract
Filter-bank Multicarrier Modulation (FBMC) is a 5G waveform candidate with improved spectral efficiency and out-of-band emissions performance compared to OFDM. To address the challenge of designing flexible hardware infrastructures for future wireless communications, this paper presents a dynamically reconfigurable FPGA-based Frequency Spreading FBMC (FS-FBMC) baseband modulator. Based on a detailed modulator datapath analysis, the proposed architecture combines static multi-mode modules with dynamic partial reconfiguration (DPR) to achieve a flexible and evolvable system. Results show that our design is resource-efficient, due to hardware virtualization. Moreover, low-latency reconfiguration of static multimode modules combined with ICAP overclocking results in submillisecond reconfiguration times which are viable in the context of flexible communication systems, such as Cognitive Radios.

Abstract
This work presents the design and analysis of a biological signal processing accelerator, including an interface controller and memory subsystem for a low-power CGRA. The controller design supports several operation modes, which can perform several applications when paired with the CGRA reconfiguration capabilities. Physical synthesis shows that the controller introduces only a 6 percent area and power overhead compared to the CGRA core, while allowing independent processing of inner loops at high frequencies and the exploitation of pipelining and parallelism. In-depth power analysis based on layout information was performed, including an evaluation of the use of power gating techniques. A practical case study (ECG signal processing) was also evaluated. © 2018 IEEE.

Abstract
Source routing (SR) minimum cost forwarding (MCF) – SRMCF – is a reactive, energy-efficient routing protocol proposed to improve the existent MCF methods utilized in heterogeneous wireless sensor networks (WSN). This paper presents an analytical analysis with experimental support that demonstrates the effectiveness of the proposed protocol. SRMCF stems from SR concepts and MCF methods exploited in ad hoc WSNs, where all unicast communications (between sensor nodes and the base station, or vice versa) use minimum cost paths. The protocol utilized in the present work was updated and now also handles link and node failures. Theoretical analysis and simulations show that the final protocol exhibits better throughput and energy consumption than MCF. Memory requirements for the routing table in the base station are also analyzed. Experimental results in a real scenario were obtained for implementations of both protocols, MCF and SRMCF, deployed in a small network of TelosB motes. Results show that SRMCF presents a 33% higher throughput and 24% less energy consumption than MCF. Extensive © 2019 River Publishers

Abstract

Abstract
In this work we present a reconfigurable and scalable custom processor array for solving optimization problems using cellular genetic algorithms (cGAs), based on a regular fabric of processing nodes and local memories. Cellular genetic algorithms are a variant of the well-known genetic algorithm that can conveniently exploit the coarse-grain parallelism afforded by this architecture. To ease the design of the proposed computing engine for solving different optimization problems, a high-level synthesis design flow is proposed, where the problem-dependent operations of the algorithm are specified in C++ and synthesized to custom hardware. A spectrum allocation problem was used as a case study and successfully implemented in a Virtex-6 FPGA device, showing relevant figures for the computing acceleration.