2020
Autores
Rocha, A; Adeli, H; Reis, LP; Costanzo, S; Orovic, I; Moreira, F;
Publicação
WorldCIST (2)
Abstract
2020
Autores
Mahata, B; Pramanik, J; van der Weyden, L; Polanski, K; Kar, G; Riedel, A; Chen, X; Fonseca, NA; Kundu, K; Campos, LS; Ryder, E; Duddy, G; Walczak, I; Okkenhaug, K; Adams, DJ; Shields, JD; Teichmann, SA;
Publicação
Nature Communications
Abstract
2020
Autores
PAULO MORAIS, E; CUNHA, CR; GOMES, JP;
Publicação
Journal of e-Learning and Higher Education
Abstract
2020
Autores
Pinheiro, G; Pereira, T; Dias, C; Freitas, C; Hespanhol, V; Costa, JL; Cunha, A; Oliveira, HP;
Publicação
SCIENTIFIC REPORTS
Abstract
2020
Autores
Paulin, N; Ferreira, JC; Cardoso, JMP;
Publicação
ACM COMPUTING SURVEYS
Abstract
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. © 2020 Association for Computing Machinery.
2020
Autores
Lotfi, M; Monteiro, C; Shafie-khah, M; Catalão, JP;
Publicação
Blockchain-based Smart Grids
Abstract
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