Cookies Policy
We use cookies to improve our site and your experience. By continuing to browse our site you accept our cookie policy. Find out More
Close
  • Menu
About

About

Graduated in Electrical and Computers Engineering (MSc degree) at the Faculty of Engineering of the University of Porto. Currently working as a Research Assistant at INESC Porto pursuing his PhD degree in Telecommunications. Shortly after my graduation, I did an internship at Xilinx Research Labs (Dublin) related with the use of FPGAs for data center architectures. Throughout my academic path, I had two experiences in foreign academic/R&D intitutions: 1) Exchange student at KTH - Royal Institute of Technology, in Sweden, during two semesters (Erasmus exchange program); 2) Master Dissertation student and later Research Assistant at FZI - Forschungszentrum Informatik am Karlsruher Institut für Technologie, in Germany, during two semesters. (Thesis title: Achieving Interoperability between SystemC and System#) I also had an Integration in Research experience at INESC Porto, whose research topic was the analysis and modelling of network traffic generated by virtual worlds.

Interest
Topics
Details

Details

Publications

2018

A parallel-pipelined OFDM baseband modulator with dynamic frequency scaling for 5G systems

Authors
Ferreira, ML; Ferreira, JC; Hübner, M;

Publication
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Abstract
5G heterogeneity will cover a huge diversity of use cases, ranging from enhanced-broadband to low-throughput and low-power communications. To address such requirements variety, this paper proposes a parallel-pipelined architecture for an OFDM baseband modulator with clock frequency run-time adaptation through dynamic frequency scaling (DFS). It supports a set of OFDM numerologies recently proposed for 5G communication systems. The parallel-pipelined architecture can achieve high throughputs at low clock frequencies (up to 520.3 MSamples/s at 160 MHz) and DFS allows for the adjustment of baseband processing clock frequency according to immediate throughput demands. The application of DFS increases the system’s power efficiency by allowing power savings up to 62.5%; the resource and latency overhead is negligible. © Springer International Publishing AG, part of Springer Nature 2018.

2017

FPGA-based implementation of a frequency spreading FBMC-OQAM baseband modulator

Authors
Carvalho, M; Ferreira, ML; Ferreira, JC;

Publication
2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Abstract

2017

Towards a Type 0 Hypervisor for Dynamic Reconfigurable Systems

Authors
Janssen, B; Korkmaz, F; Derya, H; Huebner, M; Ferreira, ML; Ferreira, JC;

Publication
2017 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)

Abstract
The usage of application-specific hardware based on Field-Programmable Gate Arrays (FPGA) has proven its benefits. Current system-on-chips, which contain FPGA fabric, supporting dynamic partial reconfiguration, enable a dynamic hardware acceleration for hardware/software co-designs. With the trend to consolidate multiple computing systems into a single system, applications with mixed criticalities can come into conflict. With our approach, we are exploring the possibility to utilize dedicated hardware for the system management and benefit from possible parallelization of applications and system management tasks.

2016

Dynamically Reconfigurable FFT Processor for Flexible OFDM Baseband Processing

Authors
Ferreira, ML; Barahimi, A; Ferreira, JAC;

Publication
2016 11TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS)

Abstract
The Physical layer architectures for the next generation of wireless devices will be characterized by a high degree of flexibility for real-time adaptation to communication conditions variability. OFDM-based architectures are strong candidates for the Physical layer implementation in 5G systems and one of the most important baseband processing operations required by this waveform is the Fast Fourier Transform (FFT). This paper proposes a dynamically reconfigurable FFT processor supporting FFT sizes and throughputs required by the most widely used wireless standards. The FFT reconfiguration was achieved by means of FPGA-based Dynamic Partial Reconfiguration (DPR) techniques, which enables run-time FFT size adaptation according to communication requirements and better resource utilization. The impact of DPR in terms of reconfiguration time and power consumption overhead was evaluated. The obtained results encourage the exploitation of DPR techniques to implement reconfigurable hardware infrastructures for OFDM baseband processing engines.

2016

Dynamically Reconfigurable LTE-compliant OFDM Modulator for Downlink Transmission

Authors
Ferreira, ML; Barahimi, A; Ferreira, JC;

Publication
2016 CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2016)

Abstract
As the number of wireless devices, services, communication standards and respective modes of operation rapidly grows, the design of reconfigurable digital baseband processing systems for radio devices becomes more important and challenging. Long Term Evolution (LTE) is among the most relevant wireless systems in 4G communications and its waveform is OFDM-based. According to the LTE mode of operation, OFDM parameters may change and influence baseband processing operations. This paper presents a dynamically reconfigurable LTE-compliant OFDM modulator for Downlink transmission able to adapt its internal hardware organization on-demand according to the digital modulation scheme and OFDM parameters, such as number of data subcarriers, IFFT size, Cyclic Prefix and window length. System reconfiguration is performed by employing FPGA-based Dynamic Partial Reconfiguration (DPR) techniques. The worst-case DPR latencies measured are 895 mu s and 1.192 ms for digital modulation and channel bandwidth adaptation, respectively. These results show that the adopted design approach is feasible in wireless baseband processing systems. Power estimations suggest that circuit specialization at run-time can potentially improve system power efficiency.