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Research Opportunity
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Research Opportunity

Telecommunications

[Open]

Work description

- Development of the digital signal processing component of the system, through the implementation in FPGA of the digital beamformer. - Implementation of a synthesizable RTL description (Verilog) of processing architectures and corresponding validation by simulation. - Development of interface between baseband modem and FPGA and interface between FPGA and RF-frontend, therefore ensuring a perfect system integration. - Writing of the grant activities report.

Academic Qualifications

PhD in in Electrical Engineering, or similar.

Minimum profile required

- Training in the development of FPGA realizations.- 1 publication in a scientific journal from the first quartile (Q1) SCOPUS, as first author, in the area of the project.

Preference factors

- Experience in digital signal processing logic architectures in FPGA. - Experience in synthesizable RTL description (Verilog) of processing architectures and corresponding validation by simulation

Application Period

Since 02 Dec 2020 to 16 Dec 2020

[Open]

Cluster / Centre

Networked Intelligent Systems / Telecommunications and Multimedia

Scientific Advisor

Luís Manuel Pessoa