Research and development of techniques to generate automatically hardware accelerators implemented in FPGAs from streams of CPU instructions obtained from program executions.
Licenciado (BSc) and Master in Informatics Engineering or in related areas
Minimum profile required
Average score of the Licenciatura (BSc) and Master greater than 14 points
- Experience in implementing techniques for code analysis, in compiler engineering tasks, knowledge and use of high-level synthesis tools, and FPGAs and hardware accelerators. - Master's Dissertation in the area of compilers and mainly in code optimizations for high-level synthesis for FPGAs;
Since 16 Nov 2020 to 30 Nov 2020
Cluster / Centre
Networked Intelligent Systems / Telecommunications and Multimedia